Re: [PATCH 3/5] irqchip/qcom-pdc: Configure PDC to pass through mode

[Maulik Shah (mkshah)]

On 3/24/2026 8:22 AM, Bjorn Andersson wrote:
> On Thu, Mar 12, 2026 at 09:26:37PM +0530, Maulik Shah wrote:
>> There are two modes PDC irqchip supports pass through mode and secondary
>> controller mode.
>>
>> All PDC irqchip supports pass through mode in which both Direct SPIs and
>> GPIO IRQs (as SPIs) are sent to GIC without latching at PDC.
>>
>> Newer PDCs (v3.0 onwards) also support additional secondary controller mode
>> where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs
>> still works same as pass through mode without latching at PDC even in
>> secondary controller mode.
>>
>> All the SoCs so far default uses pass through mode with the exception of
>> x1e. x1e PDC may be set to secondary controller mode for builds on CRD
>> boards whereas it may be set to pass through mode for IoT-EVK.
>>
>> There is no way to read which current mode it is set to and make PDC work
>> in respective mode as the read access is not opened up for non secure
>> world. There is though write access opened up via SCM write API to set the
>> mode.
>>
>> Configure PDC mode to pass through mode for all x1e based boards via SCM
>> write.
>>
> 
> You're failing to mention that the SCM interface was not present in
> initially shipping Windows firmware, which would result in you breaking
> those devices.

I will mention same in the v2 series commit message.

This series has also been tested on older firmware and the scm_write failure path is handled
properly, so existing devices will not be braked.

> 
> If you're certain that this change is available to all users, you can
> argue that this is acceptable - but omitting this from the commit
> message isn't.

Not certain. In v2 series adding the secondary mode support which allows to hit deepest low
power mode irrespective of the old/new firmware.

Thanks,
Maulik