Re: [PATCH net-next 3/5] net: phy: Add support for the ADIN1140 PHY

[Andrew Lunn]

On Thu, May 21, 2026 at 08:24:41PM +0000, Regus, Ciprian wrote:
> 
> > > +static int adin1140_phy_read_mmd(struct phy_device *phydev, int
> > devnum,
> > > +				 u16 regnum)
> > > +{
> > > +	struct mii_bus *bus = phydev->mdio.bus;
> > > +	int addr = phydev->mdio.addr;
> > > +
> > > +	return __mdiobus_c45_read(bus, addr, devnum, regnum);
> > > +}
> > > +
> > > +static int adin1140_phy_write_mmd(struct phy_device *phydev, int
> > devnum,
> > > +				  u16 regnum, u16 val)
> > > +{
> > > +	struct mii_bus *bus = phydev->mdio.bus;
> > > +	int addr = phydev->mdio.addr;
> > > +
> > > +	return __mdiobus_c45_write(bus, addr, devnum, regnum, val);
> > > +}
> > 
> > Why do these exist?
> >
> 
> The PHY is always probed over C22. Unless read_mmd()/write_mmd() are defined,
> phylib will default to indirect accesses to MMD devices. The 0xD and 0xE PHY registers
> are not implemented, so those transfers won't have any effect.

In oa_tc6_mdiobus_register() there is the comment:

       /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and
         * C45 registers space. If the PHY is discovered via C22 bus protocol it
         * assumes it uses C22 protocol and always uses C22 registers indirect
         * access to access C45 registers. This is because, we don't have a
         * clean separation between C22/C45 register space and C22/C45 MDIO bus
         * protocols. Resulting, PHY C45 registers direct access can't be used
         * which can save multiple SPI bus access. To support this feature, PHY
         * drivers can set .read_mmd/.write_mmd in the PHY driver to call
         * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c
         */

which is what you are doing.

If this was a DT driven device, you would add:

compatible = "ethernet-phy-ieee802.3-c45";

which would result in the device being probed via C45, and is_c45
would be set true.

Maybe we need to improve the situation here. We know C45 is
implemented, it is part of the standard. So maybe we need to set
is_c45?

In oa_tc6_phy_init() we already have:

tc6->phydev->is_internal = true;

what happens if we add

tc6->phydev->is_c45 = true; ?

Maybe this was discussed already once, when oa_tc6.c? I don't
remember.

	Andrew