Re: [PATCH v2 1/4] dt-bindings: PCI: renesas,r9a08g045-pcie: Add RZ/V2H(P) support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, May 19, 2026 at 7:57 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Mon, 18 May 2026 at 17:53, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Add support for the PCIe controller found on the Renesas RZ/V2H(P) SoC.
> >
> > The RZ/V2H(P) controller is similar to the RZ/G3E variant but includes
> > additional registers and configuration bits for PCIe lane control. It
> > supports multilink operation configured as either a single x4 link
> > or two independent x2 link controllers.
> >
> > Unlike earlier SoCs supported by this driver which only feature a single
> > PCIe controller, the RZ/V2H(P) SoC implements two controllers. Both
> > controllers rely on the system controller (`sysc`) for configuration,
> > but the required registers reside at different offsets for each instance.
> > To correctly identify the controller instance and map the corresponding
> > system controller registers, make the "linux,pci-domain" and "num-lanes"
> > properties mandatory for this SoC and restrict their values according to
> > the hardware capabilities.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
>
> > @@ -235,6 +238,20 @@ allOf:
> >            maxItems: 1
> >          reset-names:
> >            maxItems: 1
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g057-pcie
> > +    then:
> > +      properties:
> > +        linux,pci-domain:
> > +          enum: [0, 1]
>
> Sashiko has the following comments about this property[1]:
>
> | Is it appropriate to use linux,pci-domain to identify the hardware
> | controller instance?
> | Device Tree is designed to describe hardware rather than software policy
> | or configuration. The linux,pci-domain property is an OS-specific hint
> | used to assign logical PCI domain numbers.
> | Using it to identify hardware instances strictly couples the hardware
> | register mapping to an OS numbering scheme.
>
> and
>
> | Does limiting this to [0, 1] cause a regression for valid software
> | configurations?
> | For example, if a board with multiple PCIe controllers assigns domains 2
> | and 3 to these instances to avoid conflicts, the binding will fail
> | validation and the driver will fail to probe.
> | Could the hardware instances instead be identified via standard hardware
> | descriptive mechanisms, such as their physical base address (reg),
> | standard aliases, or by adding a phandle specifier argument to
> | renesas,sysc?
>
> dtschema/schemas/pci/pci-host-bridge.yaml states:
>
> | linux,pci-domain:
> |   description:
> |     If present this property assigns a fixed PCI domain number to a
> host bridge,
> |     otherwise an unstable (across boots) unique number will be assigned.
> |     It is required to either not set this property at all or set it for all
> |     host bridges in the system, otherwise potentially conflicting
> domain numbers
> |     may be assigned to root buses behind different host bridges.  The domain
> |     number for each host bridge in the system must be unique.
>
> In the RZ/V2H case, the number is local to the SYSC instance referenced
> by the renesas,sysc property, while linux,pci-domain is global to the
> full system by definition. Fixing the numbers to zero and one works,
> until some other controller in the system has conflicting requirements.
>
> I do see a future case where this may break: if Renesas would release a
> new SoC containing two RZ/V2H dies, there would be four PCIe controllers
> and two SYSC controllers.  This would require two PCIe controllers to
> have linux,pci-domain = <0>, and two having linux,pci-domain = <1>,
> which is not permitted.
>
Agreed.

> Hence adding a second cell to the renesas,sysc property, to specify
> the base offset of the PCIe-related registers inside SYSC seems like
> the best way to go?
>
Ok, I will change renesas,sysc to use phandle-array so that we can
pass the controller index.

Cheers,
Prabhakar