Re: [PATCH 03/11] perf/x86/intel: Update event constraints for DMR

From: Chen, Zide

Date: Tue May 19 2026 - 18:20:05 EST




On 5/15/2026 11:11 PM, Dapeng Mi wrote:
> Add missed event constraint for 0x0200 event and add comments to show
> the event names in pnc_hw_cache_extra_regs[].
>
> Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
> ---

Reviewed-by: zide.chen@xxxxxxxxx


> arch/x86/events/intel/core.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index b3ccc785a4f6..0d0edc2d1b90 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -466,11 +466,12 @@ static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
>
> static struct event_constraint intel_pnc_event_constraints[] = {
> FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> - FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
> + FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
> FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
> - FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
> + FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
> + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
> FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
> - FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
> + FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
> METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
> METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
> METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
> @@ -821,12 +822,12 @@ static __initconst const u64 pnc_hw_cache_extra_regs
> {
> [ C(LL ) ] = {
> [ C(OP_READ) ] = {
> - [ C(RESULT_ACCESS) ] = 0x4000000000000001,
> - [ C(RESULT_MISS) ] = 0xFFFFF000000001,
> + [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
> + [ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
> },
> [ C(OP_WRITE) ] = {
> - [ C(RESULT_ACCESS) ] = 0x4000000000000002,
> - [ C(RESULT_MISS) ] = 0xFFFFF000000002,
> + [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
> + [ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */
> },
> },
> };