Re: [PATCH v8] PCI: loongson: Override PCIe bridge supported speeds for Loongson-3C6000 series

[Bjorn Helgaas]

On Tue, May 19, 2026 at 10:23:22AM +0800, Xi Ruoyao wrote:
> On Mon, 2026-05-18 at 13:53 -0500, Mario Limonciello wrote:
> > > > Also, the amdgpu driver reads the value by pcie_get_speed_cap() in
> > > > amdgpu_device_partner_bandwidth(), for its dynamic adjustment of PCIe
> > > > clocks and lanes in power management. We hope this patch can prevent
> > > > similar problems in future driver changes (similar checks may be
> > > > implemented in other GPU, storage controller, NIC, etc. drivers).
> > > 
> > > Why is this paragraph here?  Is there code in
> > > amdgpu_device_partner_bandwidth() that wouldn't be needed after this
> > > patch?
> > 
> > I don't think that would be the case as this patch is a pure quirk for
> > one device.
> > 
> > The policy we have in amdgpu_device_partner_bandwidth() takes into 
> > account specifically the topology of dGPUs that have integrated PCI 
> > switches.
> > 
> > We need to look at the speed and width of the link partner connected to 
> > the switch not between the switch and the GPU PCI device.
> 
> Yes, the paragraph was intended to explain why the lower speed only
> manifests on some (not all) PCIe devices, for example amdgpu, with the
> incorrect LinkCap2 from hardware.
> 
> > > This patch updates pdev->supported_speeds, which is used by
> > > pcie_get_speed_cap(), which is in turn used by
> > > amdgpu_device_partner_bandwidth().
> > > 
> > > Is the point just that users of pcie_get_speed_cap() (currently just
> > > amdgpu, radeon, and sysfs) will now see the correct maximum link speed
> > > for Loongson-3C6000 bridges?
> > > 
> > > And the "checks" you refer to would be the tests in
> > > amdgpu_device_get_pcie_info() that use the results of
> > > pcie_get_speed_cap()?
> > 
> > I think I agree with Bjorn to drop the paragraph, it just adds confusion 
> > to the reader.
> > 
> > You can have a sentence along the lines of "Updating the speeds to the
> > correct actual support of the hardware avoids quirks in drivers 
> > consuming the speed information".
> 
> Yes, it will seem better.
> 
> Bjorn: do you need a v9 or would you just amend the message in your
> tree?

I amended the commit log:

  ...

  As a result, since commit 774c71c52aa4 ("PCI/bwctrl: Enable only if more
  than one speed is supported"), bwctrl will be disabled if there's only
  one 2.5 GT/s value in vector 'supported_speeds'.

  Manually override the 'supported_speeds' field for affected PCIe bridges
  with those found on the upstream bus to correctly reflect the supported
  link speeds.  Updating the speeds to reflect what the hardware actually
  supports avoids quirks in drivers consuming the speed information.