Re: [PATCH 3/3] arm64: dts: imx95: Add iommus property and enable SMMU

From: Frank Li

Date: Tue May 19 2026 - 14:21:16 EST


On Thu, Apr 09, 2026 at 08:00:03PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@xxxxxxx>
>
> Add iommus property for SDHC and EDMA
> Enable SMMU by default.
>
> Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> ---

Peng:
I have to drop this patch because it cause below CHECK_DTB warnings
arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dtb: dma-controller@42210000 (fsl,imx95-edma5): Unevaluated properties are not allowed ('iommus' was unexpected)
from schema $id: http://devicetree.org/schemas/dma/fsl,edma.yaml


Frank

> arch/arm64/boot/dts/freescale/imx95.dtsi | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 3e35c956a4d7af88310b3dfaef7e3d064f530e07..adcc0e1d3696b93250ab97fcac7c181b187d3d10 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -777,6 +777,7 @@ edma3: dma-controller@42210000 {
> <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> clock-names = "dma";
> + iommus = <&smmu 0x0>;
> };
>
> mu7: mailbox@42430000 {
> @@ -1242,6 +1243,7 @@ usdhc1: mmc@42850000 {
> bus-width = <8>;
> fsl,tuning-start-tap = <1>;
> fsl,tuning-step = <2>;
> + iommus = <&smmu 0x1>;
> status = "disabled";
> };
>
> @@ -1259,6 +1261,7 @@ usdhc2: mmc@42860000 {
> bus-width = <4>;
> fsl,tuning-start-tap = <1>;
> fsl,tuning-step = <2>;
> + iommus = <&smmu 0x2>;
> status = "disabled";
> };
>
> @@ -1276,6 +1279,7 @@ usdhc3: mmc@428b0000 {
> bus-width = <4>;
> fsl,tuning-start-tap = <1>;
> fsl,tuning-step = <2>;
> + iommus = <&smmu 0x3>;
> status = "disabled";
> };
> };
> @@ -1768,7 +1772,6 @@ smmu: iommu@490d0000 {
> <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>;
> interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> #iommu-cells = <1>;
> - status = "disabled";
> };
>
> pmu@490d2000 {
>
> --
> 2.37.1
>