Re: [PATCH 2/2] arm64: dts: qcom: ipq5210: Enable PCIe support

From: Manivannan Sadhasivam

Date: Tue May 19 2026 - 12:59:39 EST

On Thu, May 14, 2026 at 09:43:02AM +0530, Varadarajan Narayanan wrote:
> Add DT entries to enable the PCIe controllers found in ipq5210.
>
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 43 +++++
> arch/arm64/boot/dts/qcom/ipq5210.dtsi | 261 +++++++++++++++++++++++++++-
> 2 files changed, 302 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> index 941f866ecfe9..5e599a1cea3f 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> @@ -5,6 +5,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> #include "ipq5210.dtsi"
>
> / {
> @@ -20,6 +21,32 @@ chosen {
> };
> };
>
> +&pcie0_phy {
> + status = "okay";
> +};
> +
> +&pcie0_rp {
> + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie0 {
> + pinctrl-0 = <&pcie0_default_state>;
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> +&pcie1_rp {
> + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie1 {
> + pinctrl-0 = <&pcie1_default_state>;
> + status = "okay";
> +};
> +
> &sdhc {
> max-frequency = <192000000>;
> bus-width = <4>;
> @@ -36,6 +63,22 @@ &sleep_clk {
> };
>
> &tlmm {
> + pcie0_default_state: pcie0-default-state {
> + pins = "gpio32";
> + function = "gpio";
> + drive-strength = <6>;
> + bias-pull-down;
> + output-low;
> + };
> +
> + pcie1_default_state: pcie1-default-state {
> + pins = "gpio29";
> + function = "gpio";
> + drive-strength = <6>;
> + bias-pull-down;
> + output-low;
> + };
> +
> qup_uart1_default_state: qup-uart1-default-state {
> pins = "gpio38", "gpio39";
> function = "qup_se1";
> diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> index 3761eb03ab24..ec1c9a8c08e0 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,ipq5210-gcc.h>
> +#include <dt-bindings/interconnect/qcom,ipq5210.h>
> #include <dt-bindings/reset/qcom,ipq5210-gcc.h>
>
> / {
> @@ -13,6 +14,18 @@ / {
> interrupt-parent = <&intc>;
>
> clocks {
> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -130,6 +143,54 @@ soc@0 {
> dma-ranges = <0 0 0 0 0x10 0>;
> ranges = <0 0 0 0 0x10 0>;
>
> + pcie0_phy: phy@84000 {
> + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy",
> + "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x0 0x00084000 0x0 0x1000>;
> +
> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_PCIE0_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "pipe";
> +
> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + #clock-cells = <0>;
> + clock-output-names = "gcc_pcie0_pipe_clk_src";
> +
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + pcie1_phy: phy@f4000 {
> + compatible = "qcom,ipq5210-qmp-gen3x2-pcie-phy",
> + "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x0 0x000f4000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE1_AUX_CLK>,
> + <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_PCIE1_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "pipe";
> +
> + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>, <&gcc GCC_PCIE1_AHB_CLK>;
> + assigned-clock-rates = <20000000>, <100000000>;
> +
> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + #clock-cells = <0>;
> + clock-output-names = "gcc_pcie1_pipe_clk_src";
> +
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq5210-tlmm";
> reg = <0x0 0x01000000 0x0 0x300000>;
> @@ -146,8 +207,8 @@ gcc: clock-controller@1800000 {
> reg = <0x0 0x01800000 0x0 0x40000>;
> clocks = <&xo_board>,
> <&sleep_clk>,
> - <0>,
> - <0>,
> + <&pcie30_phy0_pipe_clk>,
> + <&pcie30_phy1_pipe_clk>,
> <0>,
> <0>;
> #clock-cells = <1>;
> @@ -299,6 +360,202 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + pcie1: pcie@50000000 {
> + compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574";
> + reg = <0x0 0x50000000 0x0 0xf1c>,
> + <0x0 0x50000f20 0x0 0xa8>,
> + <0x0 0x50001000 0x0 0x1000>,
> + <0x0 0x000f0000 0x0 0x3000>,
> + <0x0 0x50100000 0x0 0x1000>,
> + <0x0 0x000f6000 0x0 0x1000>;
> + reg-names = "dbi",
> + "elbi",
> + "atu",
> + "parf",
> + "config",
> + "mhi";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <2>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0x0 0x50200000 0x0 0x50200000 0x0 0x00100000>,
> + <0x82000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>;

<0x01000000 0x0 0x0 0x0 0x50200000 0x0 0x00100000>,
<0x02000000 0x0 0x0 0x0 0x50300000 0x0 0x0fd00000>;

> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7";
> +
> + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE1_RCHNG_CLK>,
> + <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_PCIE1_AUX_CLK>;
> +
> + clock-names = "axi_m",
> + "axi_s",
> + "axi_bridge",
> + "rchng",
> + "ahb",
> + "aux";
> +
> + resets = <&gcc GCC_PCIE1_PIPE_ARES>,
> + <&gcc GCC_PCIE1_CORE_STICKY_RESET>,
> + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>,
> + <&gcc GCC_PCIE1_AXI_S_ARES>,
> + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>,
> + <&gcc GCC_PCIE1_AXI_M_ARES>,
> + <&gcc GCC_PCIE1_AUX_ARES>,
> + <&gcc GCC_PCIE1_AHB_ARES>;
> +
> + reset-names = "pipe",
> + "sticky",
> + "axi_s_sticky",
> + "axi_s",
> + "axi_m_sticky",
> + "axi_m",
> + "aux",
> + "ahb";
> +
> + interconnects = <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>,
> + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + status = "disabled";
> +
> + pcie1_rp: pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> + phys = <&pcie1_phy>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> + };
> +
> + pcie0: pcie@70000000 {
> + compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574";
> + reg = <0x0 0x70000000 0x0 0xf1c>,
> + <0x0 0x70000f20 0x0 0xa8>,
> + <0x0 0x70001000 0x0 0x1000>,
> + <0x0 0x00080000 0x0 0x3000>,
> + <0x0 0x70100000 0x0 0x1000>,
> + <0x0 0x00086000 0x0 0x1000>;
> + reg-names = "dbi",
> + "elbi",
> + "atu",
> + "parf",
> + "config",
> + "mhi";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0x0 0x70200000 0x0 0x70200000 0x0 0x00100000>,
> + <0x82000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>;

Same as above.

- Mani

--
மணிவண்ணன் சதாசிவம்