Re: [PATCH] dma-debug: skip cacheline overlap tracking on cache-coherent architectures

[Christoph Hellwig]

On Tue, May 19, 2026 at 02:57:45PM +0500, Mikhail Gavrilov wrote:
> On Tue, May 19, 2026 at 2:28 PM Christoph Hellwig <hch@xxxxxx> wrote:
> >
> > This work is upstream, IIRC it got merged around 6.18 or 6.19.
> 
> I went through Keith's v6.18/v6.19 series -- the block-size alignment
> infrastructure is there (20a0e6276edb and surrounding), but I didn't
> find a commit that actually wires cache-line alignment as the
> requirement for non-coherent DIO (no dma_get_cache_alignment() or
> L1_CACHE_BYTES references under block/ or drivers/nvme/ in that
> range). If that enforcement is still future work building on Keith's
> infrastructure, it's orthogonal to this patch's coherent-arch
> suppression.

Sorry if I was misunderstood.  I meant the changes to move the alignment
enforcement down to the drivers was merged.  There is no code to factor
the cache line size into that for non-coherent devices.  We'd need
someone who can actually test block and file system I/O on such devices
to help with that.