Re: [PATCH v4 1/2] dt-bindings: memory: renesas,rzg3e-xspi: Add RZ/T2H and RZ/N2H support

[Krzysztof Kozlowski]

On Fri, May 15, 2026 at 12:52:01PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> 
> Document xSPI controller found on the Renesas RZ/T2H and RZ/N2H SoCs.
> The xSPI IP on these SoCs is identical to that found on the RZ/G3E SoC.
> 
> The RZ/G3E HW manual (Rev.1.15) references bridge channel 1 and its
> bits, however the hardware actually supports only a single bridge
> channel (channel 0), matching the RZ/T2H design. The references to
> channel 1 and its configuration bits will be corrected in a future
> revision of the HW manual.
> 
> Update clock/reset constraints to handle the SoC differences.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---

Wearing DT hat to fulfill the process:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>

but anyway I will be applying this.

Best regards,
Krzysztof