RE: [PATCH v3 4/5] drm: renesas: rz-du: Move mode_valid logic to per-output clock limits

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx>
> Sent: 17 May 2026 21:30
> Subject: Re: [PATCH v3 4/5] drm: renesas: rz-du: Move mode_valid logic to per-output clock limits
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Sun, May 17, 2026 at 6:59 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> > > Sent: 12 May 2026 15:41
> > > Subject: [PATCH v3 4/5] drm: renesas: rz-du: Move mode_valid logic
> > > to per-output clock limits
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Move pixel clock validation from a fixed encoder check to per-output
> > > constraints stored in rzg2l_du_output_routing.
> > >
> > > Previously, rzg2l_du_encoder_mode_valid() applied a hard-coded 83.5
> > > MHz upper limit specifically for DPAD0. This approach cannot scale
> > > across the RZ DU family because pixel clock limits vary per SoC and per output interface.
> > >
> > > Add mode_clock_min and mode_clock_max fields to
> > > rzg2l_du_output_routing so that clock constraints are expressed at
> > > the granularity of individual output interfaces rather than globally
> > > per SoC. Update
> > > rzg2l_du_encoder_mode_valid() to look up the routing entry for the
> > > active output and return MODE_CLOCK_LOW or MODE_CLOCK_HIGH when the
> > > pixel clock falls outside the declared range. A value of 0 for either field means no bound is
> enforced in that direction.
> > >
> > > Set the DPAD0 pixel clock limits for RZ/G2UL (R9A07G043U) to 20.875 MHz minimum and 83.5 MHz
> maximum.
> > > RZ/G2L and RZ/G2LC (R9A07G044) share the same DPAD0 pixel clock limits.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > > v2->v3:
> > > - Moved clock limits from device_info to output_routing to allow
> > >   per-output constraints.
> > > - Updated commit message to reflect the change in approach.
> > >
> > > v1->v2:
> > > - Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed.
> > > ---
> > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c     | 4 ++++
> > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h     | 4 ++++
> > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 6 +++++-
> > >  3 files changed, 13 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_drv.c index
> > > 0fef33a5a089..d1bc205eb5f8 100644
> > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > @@ -33,6 +33,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
> > >               [RZG2L_DU_OUTPUT_DPAD0] = {
> > >                       .possible_outputs = BIT(0),
> > >                       .port = 0,
> > > +                     .mode_clock_min = 20875,
> > > +                     .mode_clock_max = 83500,
> > >               },
> > >       },
> > >  };
> > > @@ -47,6 +49,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> > >               [RZG2L_DU_OUTPUT_DPAD0] = {
> > >                       .possible_outputs = BIT(0),
> > >                       .port = 1,
> > > +                     .mode_clock_min = 20875,
> > > +                     .mode_clock_max = 83500,
> > >               }
> > >       }
> > >  };
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_drv.h index
> > > 58806c2a8f2b..307ae70dd382 100644
> > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > @@ -30,6 +30,8 @@ enum rzg2l_du_output {
> > >   * struct rzg2l_du_output_routing - Output routing specification
> > >   * @possible_outputs: bitmask of possible outputs
> > >   * @port: device tree port number corresponding to this output
> > > route
> > > + * @mode_clock_min: minimum pixel clock in kHz
> > > + * @mode_clock_max: maximum pixel clock in kHz
> > >   *
> > >   * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data
> > >   * specify the valid SoC outputs, which CRTC can drive the output,
> > > and the type @@ -38,6 +40,8 @@ enum rzg2l_du_output {  struct rzg2l_du_output_routing {
> > >       unsigned int possible_outputs;
> > >       unsigned int port;
> > > +     int mode_clock_min;
> > > +     int mode_clock_max;
> > >  };
> > >
> > >  /*
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_encoder.c index
> > > 0e567b57a408..4af2ae09ff39 100644
> > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > @@ -50,8 +50,12 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
> > >                           const struct drm_display_mode *mode)  {
> > >       struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
> > > +     struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
> > > +     const struct rzg2l_du_output_routing *route =
> > > +&rcdu->info->routes[renc->output];
> > >
> > > -     if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
> >
> > Please retain the check for DPAD output, to avoid checking the same for DSI and LVDS.
> >
> This patch checks only for pads that have added constraints.

It will lead to two checks route->mode_clock_min and route->mode_clock_max.

Whereas by checking

if (renc->output != RZG2L_DU_OUTPUT_DPAD0) is a single check and it is meant 
for skipping DSI and LVDS as the respective encoder drivers do have mode_valid().

Cheers,
Biju