[PATCH v3 4/4] arm64: dts: qcom: sm8550: add UART11 node
From: Alexandre Hamamdjian via B4 Relay
Date: Sun May 17 2026 - 09:15:33 EST
From: Alexandre Hamamdjian <azkali.limited@xxxxxxxxx>
Add the QUPv3_2 SE3 High Speed UART (UART11) controller node and its
default pinctrl state to sm8550.dtsi, so boards can enable it through
&uart11 instead of open-coding the controller in their own dts.
Signed-off-by: Alexandre Hamamdjian <azkali.limited@xxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index a9c678fc9cb2..3e71701b18ff 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1084,6 +1084,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
status = "disabled";
};
+ uart11: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart11_default>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core", "qup-config";
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ status = "disabled";
+ };
+
i2c12: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
@@ -5102,6 +5120,14 @@ qup_uart7_default: qup-uart7-default-state {
bias-disable;
};
+ qup_uart11_default: qup-uart11-default-state {
+ /* TX, RX */
+ pins = "gpio70", "gpio71";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_uart14_default: qup-uart14-default-state {
/* TX, RX */
pins = "gpio78", "gpio79";
--
2.54.0