Re: [PATCH v5 5/7] cxl: Add CXL DVSEC reset sequence and flow orchestration

[Dan Williams (nvidia)]

Dan Williams (nvidia) wrote:
> smadhavan@ wrote:
[..]

A follow-up///

> In the short term the fastest answers to those questions is just walk
> the memdev and cxl root, in the longer term I would be open to building
> more CXL awareness into the core so that CXL reset does not need a
> driver loaded.

While I do think cxl_memdev attach is required for now, I do not think
the UABI should suffer a move if the plan is to ever support more CXL
awareness in the PCI core.

It is also the case that PCI in general wants all PCI device relative
attributes to be statically defined in pci_dev_attr_groups.

What I think this wants then is something like a "cxl" attribute group
whose visibility for now depends on the CXL core to invoke
sysfs_update_group(s) when a cxl_memdev is registered.

Then we can start to build the built-in CXL infrastructure that a
driver-less "CXL reset" capability would need. I think this looks like
HDM address space discovery is separated from 'struct cxl_decoder'
object creation and the CXL core learns to reference the common /
built-in HDM address space discovery.

The main semantic we need is that anything that tries to map CXL memory
needs to wait for a pending reset, and that reset needs to be blocked if
CXL memory is mapped.