Re: [PATCH v5 2/4] dmaengine: fsl-edma: use devm_clk_get_optional_enabled() for DMA engine clock

[Frank Li]

On Wed, May 13, 2026 at 07:23:48PM +0800, Joy Zou wrote:
> The eDMA engine clock is optional and not present on all platforms.
> Replace devm_clk_get_enabled() with devm_clk_get_optional_enabled()
> and remove FSL_EDMA_DRV_HAS_DMACLK flag to simplify clock handling.
>
> Prepare to add channel runtime pm support.
>
> Signed-off-by: Joy Zou <joy.zou@xxxxxxx>
> ---

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>

>  drivers/dma/fsl-edma-common.h |  1 -
>  drivers/dma/fsl-edma-main.c   | 22 ++++++++++------------
>  2 files changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
> index f4354b586746d64faf375cc9ce04e15a7b6d86ab..54128b3f45cb399e1c11d9f86d64adce5c65c102 100644
> --- a/drivers/dma/fsl-edma-common.h
> +++ b/drivers/dma/fsl-edma-common.h
> @@ -204,7 +204,6 @@ struct fsl_edma_desc {
>  	struct fsl_edma_sw_tcd		tcd[];
>  };
>
> -#define FSL_EDMA_DRV_HAS_DMACLK		BIT(0)
>  #define FSL_EDMA_DRV_MUX_SWAP		BIT(1)
>  #define FSL_EDMA_DRV_CONFIG32		BIT(2)
>  #define FSL_EDMA_DRV_WRAP_IO		BIT(3)
> diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
> index 87f575d6ccafff455d47f8c794a503abf97e2af1..ecd14967bfbc07d373a74790e87f9aa36b60e6c9 100644
> --- a/drivers/dma/fsl-edma-main.c
> +++ b/drivers/dma/fsl-edma-main.c
> @@ -554,7 +554,7 @@ static struct fsl_edma_drvdata imx7ulp_data = {
>  	.dmamuxs = 1,
>  	.chreg_off = EDMA_TCD,
>  	.chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
> -	.flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
> +	.flags = FSL_EDMA_DRV_CONFIG32,
>  	.setup_irq = fsl_edma2_irq_init,
>  };
>
> @@ -567,7 +567,7 @@ static struct fsl_edma_drvdata imx8qm_data = {
>  };
>
>  static struct fsl_edma_drvdata imx8ulp_data = {
> -	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
> +	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_EDMA3,
>  	.chreg_space_sz = 0x10000,
>  	.chreg_off = 0x10000,
>  	.mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
> @@ -576,14 +576,14 @@ static struct fsl_edma_drvdata imx8ulp_data = {
>  };
>
>  static struct fsl_edma_drvdata imx93_data3 = {
> -	.flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_ERRIRQ_SHARE,
> +	.flags = FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_ERRIRQ_SHARE,
>  	.chreg_space_sz = 0x10000,
>  	.chreg_off = 0x10000,
>  	.setup_irq = fsl_edma3_irq_init,
>  };
>
>  static struct fsl_edma_drvdata imx93_data4 = {
> -	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4
> +	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_EDMA4
>  		 | FSL_EDMA_DRV_ERRIRQ_SHARE,
>  	.chreg_space_sz = 0x8000,
>  	.chreg_off = 0x10000,
> @@ -593,7 +593,7 @@ static struct fsl_edma_drvdata imx93_data4 = {
>  };
>
>  static struct fsl_edma_drvdata imx95_data5 = {
> -	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 |
> +	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_EDMA4 |
>  		 FSL_EDMA_DRV_TCD64 | FSL_EDMA_DRV_ERRIRQ_SHARE,
>  	.chreg_space_sz = 0x8000,
>  	.chreg_off = 0x10000,
> @@ -733,13 +733,11 @@ static int fsl_edma_probe(struct platform_device *pdev)
>  		regs = &fsl_edma->regs;
>  	}
>
> -	if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
> -		fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
> -		if (IS_ERR(fsl_edma->dmaclk))
> -			return dev_err_probe(&pdev->dev,
> -					     PTR_ERR(fsl_edma->dmaclk),
> -					     "Missing DMA block clock.\n");
> -	}
> +	fsl_edma->dmaclk = devm_clk_get_optional_enabled(&pdev->dev, "dma");
> +	if (IS_ERR(fsl_edma->dmaclk))
> +		return dev_err_probe(&pdev->dev,
> +				     PTR_ERR(fsl_edma->dmaclk),
> +				     "Failed to get/enable DMA clock.\n");
>
>  	ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
>
>
> --
> 2.37.1
>