[PATCH 1/3] media: dt-bindings: media: renesas,fcp: Document RZ/T2H and RZ/N2H SoCs
From: Prabhakar
Date: Thu Apr 30 2026 - 06:17:16 EST
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Document the FCPVD blocks present on the RZ/T2H and RZ/N2H SoCs.
The FCPVD implementation on these SoCs is identical to that found on the
RZ/G2L family.
Update the schema to disallow the "resets" property for these SoCs,
reflecting the absence of a reset control for the FCPVD instance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/media/renesas,fcp.yaml | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.yaml b/Documentation/devicetree/bindings/media/renesas,fcp.yaml
index 5e11ae0ee456..cbb16a7a5481 100644
--- a/Documentation/devicetree/bindings/media/renesas,fcp.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,fcp.yaml
@@ -34,6 +34,8 @@ properties:
- renesas,r9a09g047-fcpvd # RZ/G3E
- renesas,r9a09g056-fcpvd # RZ/V2N
- renesas,r9a09g057-fcpvd # RZ/V2H(P)
+ - renesas,r9a09g077-fcpvd # RZ/T2H
+ - renesas,r9a09g087-fcpvd # RZ/N2H
- const: renesas,fcpv # Generic FCP for VSP fallback
reg:
@@ -66,7 +68,6 @@ required:
- reg
- clocks
- power-domains
- - resets
additionalProperties: false
@@ -83,6 +84,8 @@ allOf:
- renesas,r9a09g047-fcpvd
- renesas,r9a09g056-fcpvd
- renesas,r9a09g057-fcpvd
+ - renesas,r9a09g077-fcpvd
+ - renesas,r9a09g087-fcpvd
then:
properties:
clocks:
@@ -94,6 +97,19 @@ allOf:
clocks:
maxItems: 1
clock-names: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g077-fcpvd
+ - renesas,r9a09g087-fcpvd
+ then:
+ properties:
+ resets: false
+ else:
+ required:
+ - resets
examples:
# R8A7795 (R-Car H3) FCP for VSP-D1
--
2.54.0