RE: [PATCH v3 2/8] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 28 April 2026 14:16
> Subject: Re: [PATCH v3 2/8] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC
> 
> Hi Biju,
> 
> On Tue, 17 Mar 2026 at 11:16, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add documentation for the pin controller found on the Renesas RZ/G3L
> > (R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has
> > more pins.
> >
> > Also add header file similar to RZ/G3E and RZ/V2H as it has alpha
> > numeric ports.
> >
> > Document renesas,clonech property for controlling clone channel
> > control register located on SYSC IP block on RZ/G3L SoC.
> >
> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
> > @@ -0,0 +1,39 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * This header provides constants for Renesas RZ/G3L family pinctrl bindings.
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corp.
> > + *
> > + */
> > +
> > +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
> > +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
> > +
> > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > +
> > +/* RZG3L_Px = Offset address of PFC_P_mn  - 0x22 */
> > +#define RZG3L_P2       2
> > +#define RZG3L_P3       3
> > +#define RZG3L_P4       4
> 
> GPIO P4x do not seem to exist, so drop this line?

OK, will drop this line.

Cheers,
Biju