[PATCH v1 2/3] pinctrl: qcom: lpass-lpi: Fix GPIO register access helper return types
From: Ajay Kumar Nandam
Date: Mon Apr 13 2026 - 08:23:28 EST
The LPI GPIO register access helpers previously returned the value from
ioread32(), even though their return type was int. This mixes data
return with status and is inconsistent with common kernel helper
conventions.
Rework lpi_gpio_read() and lpi_gpio_write() to return an int status and
use output parameters to pass register values. Update all callers to
match the new helper interface.
This change fixes the helper API and resulting call sites without
intending any functional change in GPIO or pinctrl behavior.
Signed-off-by: Ajay Kumar Nandam <ajay.nandam@xxxxxxxxxxxxxxxx>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 66 +++++++++++++++++-------
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 6d50e06ef..d108e7321 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -39,22 +39,26 @@ struct lpi_pinctrl {
};
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
- unsigned int addr)
+ unsigned int addr, u32 *val)
{
u32 pin_offset;
+ int ret;
if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)
pin_offset = state->data->groups[pin].pin_offset;
else
pin_offset = LPI_TLMM_REG_OFFSET * pin;
- return ioread32(state->tlmm_base + pin_offset + addr);
+ *val = ioread32(state->tlmm_base + pin_offset + addr);
+
+ return 0;
}
static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr, unsigned int val)
{
u32 pin_offset;
+ int ret;
if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)
pin_offset = state->data->groups[pin].pin_offset;
@@ -107,7 +111,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
{
struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct lpi_pingroup *g = &pctrl->data->groups[group];
- u32 val;
+ u32 val, io_val;
+ int ret;
int i, pin = g->pin;
for (i = 0; i < g->nfuncs; i++) {
@@ -119,7 +124,9 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
return -EINVAL;
mutex_lock(&pctrl->lock);
- val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
+ ret = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val);
+ if (ret)
+ goto out_unlock;
/*
* If this is the first time muxing to GPIO and the direction is
@@ -129,24 +136,28 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
*/
if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
!test_and_set_bit(group, pctrl->ever_gpio)) {
- u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);
+ ret = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val);
+ if (ret)
+ goto out_unlock;
if (io_val & LPI_GPIO_VALUE_IN_MASK) {
if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
- lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
- io_val | LPI_GPIO_VALUE_OUT_MASK);
+ ret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
+ io_val | LPI_GPIO_VALUE_OUT_MASK);
} else {
if (io_val & LPI_GPIO_VALUE_OUT_MASK)
- lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
- io_val & ~LPI_GPIO_VALUE_OUT_MASK);
+ ret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
+ io_val & ~LPI_GPIO_VALUE_OUT_MASK);
}
}
u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
- lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
+ ret = lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
+
+out_unlock:
mutex_unlock(&pctrl->lock);
- return 0;
+ return ret;
}
static const struct pinmux_ops lpi_gpio_pinmux_ops = {
@@ -165,8 +176,11 @@ static int lpi_config_get(struct pinctrl_dev *pctldev,
int is_out;
int pull;
u32 ctl_reg;
+ int ret;
- ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
+ ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg);
+ if (ret)
+ return ret;
is_out = ctl_reg & LPI_GPIO_OE_MASK;
pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
@@ -293,17 +307,22 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
}
mutex_lock(&pctrl->lock);
- val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
+ ret = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val);
+ if (ret) {
+ mutex_unlock(&pctrl->lock);
+ goto out_unlock;
+ }
u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
LPI_GPIO_OUT_STRENGTH_MASK);
u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
- lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
- mutex_unlock(&pctrl->lock);
+ ret = lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
- return 0;
+out_unlock:
+ mutex_unlock(&pctrl->lock);
+ return ret;
}
static const struct pinconf_ops lpi_gpio_pinconf_ops = {
@@ -352,9 +371,13 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip,
static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
{
struct lpi_pinctrl *state = gpiochip_get_data(chip);
+ u32 val;
+ int ret;
- return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
- LPI_GPIO_VALUE_IN_MASK;
+ ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val);
+ if (ret)
+ return ret;
+ return val & LPI_GPIO_VALUE_IN_MASK;
}
static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
@@ -387,6 +410,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,
int drive;
int pull;
u32 ctl_reg;
+ int ret;
static const char * const pulls[] = {
"no pull",
@@ -397,7 +421,11 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,
pctldev = pctldev ? : state->ctrl;
pindesc = pctldev->desc->pins[offset];
- ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
+ ret = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg);
+ if (ret) {
+ seq_printf(s, " %-8s: <read error %d>", pindesc.name, ret);
+ return;
+ }
is_out = ctl_reg & LPI_GPIO_OE_MASK;
func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
--
2.34.1