Re: [PATCH 1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties

[Xilin Wu]

On 4/13/2026 4:41 PM, Uwe Kleine-König wrote:
> Hello,
>
> On Mon, Apr 06, 2026 at 11:50:01PM +0800, Xilin Wu wrote:
> > The clk-pwm driver cannot produce constant output levels (0% or 100%
> > duty cycle, or disabled state) through the clock hardware alone - the
> > actual pin level when the clock is off is undefined and
> > hardware-dependent.
> >
> > Document optional gpios, pinctrl-names, pinctrl-0, and pinctrl-1
> > properties that allow the driver to switch the pin between clock
> > function mux (for normal PWM output) and GPIO mode (to drive a
> > deterministic constant level).
> >
> > Signed-off-by: Xilin Wu <sophon@xxxxxxxxx>
> > ---
> >   Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++++++++++++++-
> >   1 file changed, 35 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
> > index ec1768291503..2a0e3e02d27b 100644
> > --- a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
> > +++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
> > @@ -15,6 +15,11 @@ description: |
> >     It's often possible to control duty-cycle of such clocks which makes them
> >     suitable for generating PWM signal.
> >   
> > +  Optionally, a GPIO and pinctrl states can be provided. When a constant
> > +  output level is needed (0%, 100%, or disabled), the pin is switched to
>
> A constant output isn't needed when disabled. The state is undefined
> then. A plain clk_disable() is fine then.
>
> Best regards
> Uwe

Ack. I will change the binding description and the driver behavior in 
the next revision.

Thank you for the review.

--
Best regards,
Xilin Wu <sophon@xxxxxxxxx>