Re: [PATCH v4 04/12] ASoC: rsnd: Add RZ/G3E SoC probing and register map

[Kuninori Morimoto]

Hi John

Thank you the patch

> RZ/G3E audio subsystem has a different register layout compared to
> R-Car Gen2/Gen3/Gen4, as described below:
> 
> - Different base address organization (SCU, ADG, SSIU, SSI as
>   separate regions accessed by name)
> - Additional registers: AUDIO_CLK_SEL3, SSI_MODE3, SSI_CONTROL2
> - Different register offsets within each region
> 
> Add RZ/G3E SoC's audio subsystem register layouts and probe support.
> 
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> ---
(snip)
> +	/*
> +	 * Flags layout: 0x....DCBA
> +	 *
> +	 * A (bits  3: 0): R-Car generation (Gen1/Gen2/Gen3/Gen4)
> +	 * B (bits  7: 4): R-Car SoC variant (e.g. SOC_E for E1/E2/E3)
> +	 * C (bits 11: 8): RZ series generation
> +	 * D (bits 15:12): RZ series SoC identifier (e.g. RZG3E)

Thank you for adding layout.
But "(bits ...)" and last e.g "(...)" are not needed.

	A: R-Car generation
	B: R-Car SoC identifier
	C: RZ series generation
	D: RZ series SoC identifier

> v4:
> - Fix RSND_SOC_MASK to (0xF << 4) to avoid overlap with RSND_RZ_MASK
> - Add comment documenting flag nibble layout
(snip)
> -#define RSND_SOC_MASK	(0xFF << 4)
> +#define RSND_SOC_MASK	(0xF << 4)  /* nibble B */

This patch should be separate as bug-fix patch ?

Thank you for your help !!

Best regards
---
Kuninori Morimoto