Re: [PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Manivannan Sadhasivam]

On Sun, 05 Apr 2026 15:41:52 +0000, Yao Zi wrote:
> After talking to Inochi privately, I'll take the patch instead.
> 
> This series defines quirk flags for Cadence PCIe host driver to allow
> disabling advertisement of ASPM L0s/L1 states by overriding LNKCAP
> register, and set them in SG2042 PCIe driver since SG2042's
> implementation is broken.
> 
> [...]

Applied, thanks!

[1/2] PCI: cadence: Add flags for disabling ASPM support advertisement
      commit: 7336e9edaf19d6710b93cc1232270361a20891be
[2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
      commit: a4c1e32555ba488e163b88765de739c872da340f

Best regards,
-- 
Manivannan Sadhasivam <mani@xxxxxxxxxx>