RE: [PATCH v5 6/6] phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920

[Pritam Manohar Sutar]

Hi Vinod, 

> -----Original Message-----
> From: Vinod Koul <vkoul@xxxxxxxxxx>
> Sent: 19 August 2025 12:25 PM
> To: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>
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> Subject: Re: [PATCH v5 6/6] phy: exynos5-usbdrd: support SS combo phy for
> ExynosAutov920
> 
> On 18-08-25, 13:11, Pritam Manohar Sutar wrote:
> 
> > > > +	/* check cr_para_ack*/
> > > > +	cnt = 0;
> > > > +	do {
> > > > +		/*
> > > > +		 * data symbols are captured by phy on rising edge
of the
> > > > +		 * tx_clk when tx data enabled.
> > > > +		 * completion of the write cycle is acknowledged by
> > assertion
> > > > +		 * of the cr_para_ack.
> > > > +		 */
> > > > +		exynosautov920_usb31drd_cr_clk(phy_drd, true);
> > > > +		reg = readl(reg_phy +
> > > EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> > > > +		if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK))
> > > > +			break;
> > > > +
> > > > +		exynosautov920_usb31drd_cr_clk(phy_drd, false);
> > > > +
> > > > +		/*
> > > > +		 * wait for minimum of 10 cr_para_clk cycles after
phy reset
> > > > +		 * is negated, before accessing control regs to
allow for
> > > > +		 * internal resets.
> > > > +		 */
> > > > +		cnt++;
> > > > +	} while (cnt < 10);
> > > > +
> > > > +	if (cnt == 10)
> > > > +		dev_dbg(dev, "CR write failed to 0x%04x\n", addr);
> > >
> > > Not error?
> >
> > This is only for debugging purpose. It is not considered as error.
> 
> Write failed is not an error? If this code is only for debug, pls drop it.

Sure. will drop it. 

> 
> --
> ~Vinod

Regards,
Pritam