[PATCH 0/4] irqchip: add EyeQ5 PCIe MSI controller

From: Gregory CLEMENT

Date: Wed Oct 28 2026 - 12:05:40 EST


Hello,

This series adds support for the MSI controller present in the
Mobileye EyeQ5 PCIe ports.

Although the driver uses the standard MSI library, the EyeQ5 hardware
has several specific features. First, each PCIe port has its own MSI
controller, which snoops the MSI write TLPs that the port receives. A
port supports a maximum of 4 MSI vectors, and the memory-region
property gives the base address of the doorbell window. In addition,
the GCSR mode selects the role: in root complex mode the driver
registers a PCI MSI parent, while in endpoint mode it registers a
platform MSI parent. The last specific point is that the driver uses
the snooper domain as a chained controller on one GIC interrupt.

The series adds the binding document, the irqchip driver, the EyeQ5
DTS changes, and the MAINTAINERS entry. In particular, the DTS changes
add the two MSI controllers to the EyeQ5 SoC.

I tested the series with two EyeQ5 SoCs connected by a PCIe link, with
one SoC acting as the host and the other as the endpoint. The
pci_endpoint_test kselftest passed the MSIX_TEST, MSI_TEST, and
DOORBELL_TEST cases.

Grégory

Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
---
Gregory CLEMENT (4):
dt-bindings: interrupt-controller: add Mobileye EyeQ5 PCIe MSI controller
irqchip: irq-eyeq5-msi: add EyeQ5 PCIe MSI controller driver
MIPS: dts: eyeq5: add MSI controllers
MAINTAINERS: add EyeQ5 MSI controller entry

.../interrupt-controller/mobileye,eyeq5-msi.yaml | 120 ++++++
MAINTAINERS | 2 +
arch/mips/Kconfig | 1 +
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 30 ++
drivers/irqchip/Kconfig | 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eyeq5-msi.c | 474 +++++++++++++++++++++
7 files changed, 633 insertions(+)
---
base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222
change-id: 20261028-eyeq5_msi-86aa1d590684

Best regards,
--
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com