Re: [PATCH 0/6] MIPS: Ingenic: Add XBurst / XBurst II infrastructure and SoC support

[H. Nikolaus Schaller]

Hi Olivier, Thomas,

> Am 27.10.2026 um 22:08 schrieb Olivier Louvignes <olivier@xxxxxxxxx>:
> 
> Hi Nikolaus, Thomas,
> 
> Patches 2 and 3 overlap my cpu-probe v2, sent the same day with
> Nikolaus' Co-developed-by:
> https://lore.kernel.org/all/20261025073146.25326-1-olivier@xxxxxxxxx/
> 
> Both add PRID_IMP_XBURST (0x0000), so only one of them can be applied
> as it is.
> 
> They also handle the X1600 differently. Mine puts PRID_IMP_XBURST on
> the PRID_IMP_XBURST_REV2 path (write-combine through
> _CACHE_CACHABLE_WA, as for the X1830), as the Letux commits
> ee3e4e8baeb6 and b799b9a5e4d3 do. Patch 3 here gives it a case of its
> own with _CACHE_UNCACHED_ACCELERATED.

and in addition presents a different __cpu_name.

I am not sure yet which one is better and more correct regarding the
_CACHE handling. Maybe Paul Boddie can comment?

> 
> Tested on a HiBy R1 (X1600) with the REV2 path: it reports "00d00000
> (Ingenic XBurst)" and boots to userspace.
> 
> Nikolaus, which handling do you want for the X1600? If it is yours, I
> will drop my patch.

I am currently working in the feedback that we have received and
the plan is to submit a V2 soon.

The same is planned for the CGU series where I want to also include
jz4730/x2000/x2600 patches.

Best regards,
Nikolaus