Re: [PATCH v2 5/6] media: qcom: camss: sm8250: set the VFE AREG clock rate from the VFE

[Atanas Filipov]

On 26/10/2026 09:22, Bryan O'Donoghue wrote:
> Why is 100MHz a problem and if it is, why not just fix to 400MHz ?

100 MHz is not a problem by itself, and I see no failure from it.

With the rate ranges from 4/6, VFE0 at the CSID test pattern sets the
fast AHB source to 400 MHz; starting a sensor stream on VFE1 then sets
it to 100 MHz under the running VFE0, as the two AREG clocks are
separate clocks and their floors are not aggregated. All frames are
still captured.

v3 will list a single 400 MHz rate for the VFE AREG clocks, so neither
VFE lowers the source under the other.

Regards,
Atanas