Re: [PATCH v2 4/6] media: qcom: camss: share VFE clock sources by the highest rate

[Bryan O'Donoghue]

On 24/10/2026 10:40, Atanas Filipov wrote:
> Clocks of different VFEs can be fed by one clock source, and each VFE
> sets such a source to the rate it needs. A VFE started later at a lower
> rate then lowers the source under a VFE that is still running.
> 
> For example, on SM8250 the two VFE Lite share one core clock source,
> which the VFE sets to 400 or 480 MHz from the pixel rate. With VFE Lite
> 0 streaming the CSID test pattern at 480 MHz, starting an imx577 stream
> on VFE Lite 1 sets the shared source to 400 MHz under the running VFE
> Lite 0.
> 
> Group the VFE clocks with rate tables by their clock source at probe
> time. A source shared by several VFEs follows the highest rate requested
> by its running VFEs and drops to the highest remaining one when a VFE is
> powered off; with no VFE left it keeps its rate, as it may feed
> consumers outside CAMSS. A source used by a single VFE is dropped to its
> lowest rate on power off. Clocks whose rate the VFE does not set are
> left untouched.
> 
> In the example above the shared source stays at 480 MHz until VFE Lite
> 0 stops, and then drops to the 400 MHz still requested by VFE Lite 1.
> 
> Grouping is enabled through the vfe_clock_domains resource flag, so far
> only on SM8250. The current parent of an RCG depends on its last rate,
> so other SoCs keep setting their VFE clocks directly.
> 
> Signed-off-by: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>
I think this patch can be dropped.

clk_set_rate_range() is a CCF provided aggregator which will allow a VFE 
or another consumer of the same clock to set an effective floor - 
without having a driver-specific voting framework.

/* vfe_get() */
ret = clk_set_rate_range(clock->clk, rate, ULONG_MAX);

/* vfe_put() */
clk_set_rate_range(clock->clk, 0, ULONG_MAX);

This should subtract:

- camss_clock_domain
- camss_clock_vote
- camss_init_clock_domains()
- Associated boiler-plate code, mutexes etc

This holds for camnoc_axi and vfe_lite clocks.

On release, relax the range first and then clk_set_rate() to the lowest
listed rate explicitly.

Bundle that into patch #6, a driver-specific clock aggregation mechanism 
isn't required.

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bod