Re: [PATCH] clk: tegra: Fix Tegra114 MIPI calibration clock parent

[Patrick Fischer]

On Wed, Sep 30, 2026 at 02:18:34PM +0900, Mikko Perttunen wrote:
> Register the gate with pll_p_out3 as its parent. Also drop
> CLK_SET_RATE_PARENT at the same time: the parent canonically runs at
> 72 MHz so we shouldn't change the rate.

I ran into the same problem on a Tegra Note 7 (P1640) and ended up with
the identical change. Before it, every DSI enable logged

  tegra-dsi 54300000.dsi: MIPI calibration failed: -110

and enabling PLL_P_OUT3 by hand made it go away. With this patch there
is no timeout at boot or across DPMS off/on cycles.

Tested-by: Patrick Fischer <admin@xxxxxxxxxxxxxxxxxx> # Tegra Note 7 (P1640)

While testing I also found that tegra114_mipi_power_down() never drops
the clock enable it takes, so with this patch PLL_P_OUT3 stays on after
the first DPMS off. I sent a fix for that:

https://lore.kernel.org/all/20261025-upstream-host1x-mipi-clk-v1-1-6bc6e755b4cb@xxxxxxxxxxxxxxxxxx/

Thanks,
Patrick