[PATCH 0/2] ASoC: es8328: enable capture on the ES8388

[Bob Hui]

The es8328 driver never touches a register at probe time: it enables the
supplies and the clock and leaves the codec in whatever state it is in.
On a board where this driver is the only thing that configures the codec,
userspace ends up dealing with the reset values, and one of them makes the
capture path unusable.

Patch 1 describes the documented power-on values in the regmap, so the
cache matches the chip instead of being filled in lazily on first access.

Patch 2 sets SLRCK on the ES8388.  The chip has a single LRCK pin, and
without SLRCK the ADC never gets a frame clock: capture records digital
silence while playback works, which makes it look like a hardware fault.

Both were found while bringing up a QuarkPi-CA2 (RK3588S, ES8388) on v7.3.
Playback was fine from the start; capture delivered digital silence with no
noise floor at all, which turned out to be the missing frame clock.  The
same board records normally on the vendor 5.10 stack.

The ADC digital volumes still power up at -96 dB.  That is deliberately
left to userspace (UCM or an alsactl state file) rather than baked into the
driver, since the level is a system policy decision.

One documented value does not match the silicon: registers 0x1a/0x1b (DAC
digital volume) are documented to reset to 0xc0, but the ES8388 on this
board reads back 0x28 after a cold boot, and the driver never writes them.
Patch 1 keeps the documented values; if the measured ones are preferred,
those two entries can simply be dropped.

Assisted-by: Hermes:deepseek-v4-flash
Signed-off-by: Bob Hui <bg9oxa@xxxxxxx>
---
Bob Hui (2):
      ASoC: es8328: describe the power-on register values in the regmap
      ASoC: es8328: set SLRCK for the ES8388

 sound/soc/codecs/es8328.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)
---
base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222
change-id: 20261024-es8328-vol-init-6a52c17897cd

Best regards,
--  
Bob Hui <bg9oxa@xxxxxxx>