[PATCH 0/3] Fix the ENCP clock select field on GXBB, G12A and S4

[Carlo Caione]

The GXBB, G12A and S4 clock drivers describe the ENCP clock select with
the field of the ENCT one, VID_CLK_DIV[23:20], instead of [27:24]. Fix
it in the three drivers.

Signed-off-by: Carlo Caione <ccaione@xxxxxxxxxxxx>
---
Carlo Caione (3):
      clk: meson: gxbb: fix ENCP clock selection
      clk: meson: g12a: fix ENCP clock selection
      clk: meson: s4: fix ENCP clock selection

 drivers/clk/meson/g12a.c           | 2 +-
 drivers/clk/meson/gxbb.c           | 2 +-
 drivers/clk/meson/s4-peripherals.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
---
base-commit: 363f97a1ce635b86be7fd263d56a040fbd87bdbb
change-id: 20261022-upstream-clk-encp-sel-shift-fde7ac3b8ce7

Best regards,
--  
Carlo Caione <ccaione@xxxxxxxxxxxx>