Re: [PATCH 05/10] clk: qcom: cpu-8996: move off the ACD leg while the PLL speeds up

[Konrad Dybcio]

On 10/20/26 12:10 PM, Dmitry Baryshkov wrote:
> On Tue, Oct 20, 2026 at 08:52:49AM +0200, Konrad Dybcio wrote:
>> On 10/19/26 3:41 PM, Dmitry Baryshkov wrote:
>>> The MSM8996 CPU clusters sometimes run at half the rate they report
>>> after going up between two frequencies above 600 MHz, and stay there
>>> until the cluster drops below 600 MHz. The PLL, the muxes and the rest
>>> of the cluster clock registers are all as expected: it is the ACD that
>>> latches at half the rate when the PLL is reprogrammed to a higher rate
>>> underneath it, and selecting the ACD leg again clears it. The driver
>>> only moves off the ACD leg when going below 600 MHz.

[...]

> Downstream isn't keeping the main output below 1190.4 either. After
> pre_set_rate(), cpu_clk_8996_set_rate() asks the HF mux for the target
> rate, which makes mux_set_rate() set the PLL rate and then switch the mux.
> So the main output follows the PLL up to new/2, e.g. 1075.2 MHz on the
> way to 2150.4 MHz, on every increase above 1190.4 MHz.
> 
> The main difference is where the cluster waits before the PLL moves: downstream
> first lowers the PLL to 1190.4 MHz and parks the output at 595.2 MHz, while
> this patch parks it at old/2. Both are lower than the target rate. Following
> the downstream approach would mean reprogramming the PLL from inside the pmux
> notifier while CCF is changing the rate of the same tree, which feels incorrect
> to me. Also it wouldn't lower the peak.

Acked-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>

Konrad