Re: [PATCH v4] gpio: mvebu: fix Armada XP per-CPU mask register save/restore

[Bartosz Golaszewski]

On Mon, 19 Oct 2026 01:01:17 +0200, Rosen Penev <rosenp@xxxxxxxxx> said:
> The Armada XP variant keeps the per-CPU edge/level mask registers in a
> second I/O window (percpu_regs) rather than in the main GPIO window.
> The suspend and resume paths however read and wrote them through
> mvchip->regs with the per-CPU offsets, which hits the global
> GPIO_EDGE_MASK / GPIO_LEVEL_MASK registers instead. Per-CPU mask state
> was therefore lost across suspend/resume, so a level line could end up
> unmasked behind genirq's back and trigger an interrupt storm once
> interrupts are re-enabled.
>
> Use mvchip->percpu_regs for the Armada XP per-CPU mask registers in
> both the suspend save and the resume restore paths, matching the
> mask/unmask handlers and the probe-time masking.
>
> Fixes: b5b7b487431b ("gpio: mvebu: add suspend/resume support")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Rosen Penev <rosenp@xxxxxxxxx>
> ---
>  v4: rebase again
>  v3: rebase again
>  v2: rebase

Are you rebasing it on top of the gpio/for-next branch of the GPIO git tree
as indicated in MAINTAINERS? Because this still fails to apply. :(

Bart