Re: [PATCH 2/4] soc: qcom: llcc: add LCP/SRP DDR DRAM ECC register offsets

[Krzysztof Kozlowski]

On Wed, Oct 14, 2026 at 09:26:17PM +0530, Faiyaz Mohammed wrote:
> Add LCP/SRP ECC register offsets to struct llcc_edac_reg_offset and
> create llcc_lcp_srp_edac_reg_offset for QCM2390, leaving the shared
> llcc_v2_1_edac_reg_offset table unchanged. Switch shikra_cfg to the
> new table so other platforms with the same block can reuse it.
> 
> Add lcp_irq to struct llcc_drv_data and retrieve the optional second
> interrupt in qcom_llcc_probe(), propagating non-absence errors so the
> driver defers correctly.
> 
> Signed-off-by: Faiyaz Mohammed <faiyaz.mohammed@xxxxxxxxxxxxxxxx>
> ---
>  drivers/soc/qcom/llcc-qcom.c       | 45 ++++++++++++++++++++++++++++++++++++--
>  include/linux/soc/qcom/llcc-qcom.h | 13 +++++++++++
>  2 files changed, 56 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index d7a42a8040a1..39e0da14b36d 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -4509,6 +4509,41 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
>  	.drp_ecc_db_err_syn0 = 0x52120,
>  };
>  
> +static const struct llcc_edac_reg_offset llcc_lcp_srp_edac_reg_offset = {
> +	.trp_ecc_error_status0 = 0x20344,
> +	.trp_ecc_error_status1 = 0x20348,
> +	.trp_ecc_sb_err_syn0 = 0x2034c,
> +	.trp_ecc_db_err_syn0 = 0x20370,
> +	.trp_ecc_error_cntr_clear = 0x20440,
> +	.trp_interrupt_0_status = 0x20480,
> +	.trp_interrupt_0_clear = 0x20484,
> +	.trp_interrupt_0_enable = 0x20488,
> +
> +	/* LLCC Common registers */
> +	.cmn_status0 = 0x3400c,
> +	.cmn_interrupt_0_enable = 0x3401c,
> +	.cmn_interrupt_1_enable = 0x3402c,
> +	.cmn_interrupt_2_enable = 0x3403c,
> +
> +	/* LLCC DRP registers */
> +	.drp_ecc_error_cfg = 0x50000,
> +	.drp_ecc_error_cntr_clear = 0x50004,
> +	.drp_interrupt_status = 0x50020,
> +	.drp_interrupt_clear = 0x50028,
> +	.drp_interrupt_enable = 0x5002c,
> +	.drp_ecc_error_status0 = 0x520f4,
> +	.drp_ecc_error_status1 = 0x520f8,
> +	.drp_ecc_sb_err_syn0 = 0x520fc,
> +	.drp_ecc_db_err_syn0 = 0x52120,
> +
> +	/* LCP/SRP DDR DRAM ECC registers */
> +	.lcp_srp_ecc_error_cntr_clear = 0x59004,
> +	.lcp_srp_ecc_error_status1 = 0x59010,
> +	.lcp_srp_interrupt_status = 0x59070,
> +	.lcp_srp_interrupt_clear = 0x59074,
> +	.lcp_srp_interrupt_enable = 0x59078,
> +};
> +
>  static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = {
>  	.trp_ecc_error_status0 = 0x47448,
>  	.trp_ecc_error_status1 = 0x47450,
> @@ -4767,7 +4802,7 @@ static const struct qcom_llcc_config shikra_cfg[] = {
>  		.sct_data	= shikra_data,
>  		.size		= ARRAY_SIZE(shikra_data),
>  		.reg_offset	= llcc_v2_1_reg_offset,
> -		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +		.edac_reg_offset = &llcc_lcp_srp_edac_reg_offset,
>  		.irq_configured = true,
>  	},
>  };
> @@ -5798,7 +5833,13 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>  	if (drv_data->ecc_irq < 0 && drv_data->ecc_irq != -ENXIO)
>  		return dev_err_probe(&pdev->dev, drv_data->ecc_irq,
>  				     "failed to get IRQ resource\n");
> -
> +	if (cfg->edac_reg_offset && cfg->edac_reg_offset->lcp_srp_interrupt_enable) {
> +		drv_data->lcp_irq = platform_get_irq_optional(pdev, 1);

Why do you exactly require interrupt-names?

Best regards,
Krzysztof