[RFC PATCH 53/55] KVM: SVM: Hedge the v_tpr_entry comment

[David Woodhouse]

From: David Woodhouse <dwmw@xxxxxxxxxxxx>

The comment claimed V_TPR "differs, i.e. when the guest wrote CR8":
differing implies a write, but a write does not imply differing. A
same-value CR8 write is invisible to the back-sync, so TPR[3:0]
survives where the architectural write would clear it — a documented
tradeoff of commit f34c595cb8a5 ("KVM: SVM: Keep TPR[3:0] across
exits without a guest CR8 write"), which deserves stating at the
field rather than only in that commit's message. No functional
change.

Signed-off-by: David Woodhouse <dwmw@xxxxxxxxxxxx>
Assisted-by: LLM
---
 arch/x86/kvm/svm/svm.h | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 746a2ae98c4c..24d34697fe65 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -319,9 +319,13 @@ struct vcpu_svm {
 	/*
 	 * V_TPR value written by sync_lapic_to_cr8() on the last entry.
 	 * sync_cr8_to_lapic() pushes V_TPR back into the APIC only when it
-	 * differs, i.e. when the guest wrote CR8 in guest mode: V_TPR holds
-	 * TPR[7:4] only, so an unconditional back-sync would zero TPR[3:0]
-	 * after every exit, losing the low nibble of an APIC TASKPRI write.
+	 * differs: V_TPR holds TPR[7:4] only, so an unconditional back-sync
+	 * would zero TPR[3:0] after every exit, losing the low nibble of an
+	 * APIC TASKPRI write.  A differing V_TPR implies a guest CR8 write,
+	 * but not the converse: a CR8 write of the same value is
+	 * indistinguishable from no write, so TPR[3:0] survives it where
+	 * the architectural write (and the intercepted path through
+	 * kvm_lapic_set_tpr()) would clear it.
 	 */
 	u8 v_tpr_entry;
 
-- 
2.50.1