Re: [PATCH net-next v6 4/9] net: dsa: realtek: rtl8365mb: set RGMII mode for family D

[Linus Walleij]

On Fri, Oct 16, 2026 at 3:04 AM Mieczyslaw Nalewaj <namiltd@xxxxxxxxx> wrote:

> On family D, RGMII on extension interface 1 needs two things that the
> other families do not: the EXT1 RGMII TX clock delay field in
> EXT_TXC_DLY (0x13f9, bits [5:3]) must be cleared, and the pin mux in
> the top-level configuration register must be set up.
>
> The vendor RGMII setup for EXT1 clears the RGMII field of EXT_TXC_DLY
> (0x13f9, bits [5:3]) in addition to programming TXDELAY in RGMXF.
> Do the same. The init jam table writes 0x0090 to this register, which
> leaves the field at 2, so without the clear an extra TX delay would be
> applied on top of tx-internal-delay-ps. Clearing it makes
> tx-internal-delay-ps the only source of TX delay.
>
> If the internal MAC4 block occupies extension 1, do not advertise RGMII
> for port 7 in phylink_get_caps(), so the configuration is refused before
> any EXT1 register is touched. This mirrors the vendor RTL8367D API, which
> returns an error for RGMII on port 7 when UTP port 4 uses the RGMII
> interface. Otherwise bind the RGMII/MII pins to MAC7. SerDes 1, which
> shares the pins, is always disabled.
>
> The family D branch is not reachable until the chip table entry is
> added in the last patch.
>
> Signed-off-by: Mieczyslaw Nalewaj <namiltd@xxxxxxxxx>

Looks good to me.
Reviewed-by: Linus Walleij <linusw@xxxxxxxxxx>

Yours,
Linus Walleij