Re: [PATCH v3 24/27] KVM: nSVM: Flush L2's ASID when emulating INVLPGA

[Jim Mattson]

On Thu, Oct 15, 2026 at 5:53 PM Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
>
> On Thu, Oct 15, 2026, Yosry Ahmed wrote:
> > On Thu, Oct 15, 2026 at 4:37 PM Jim Mattson <jmattson@xxxxxxxxxx> wrote:
> > > > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> > > > index 8f2542357e78d..436d13f106369 100644
> > > > --- a/arch/x86/kvm/svm/svm.c
> > > > +++ b/arch/x86/kvm/svm/svm.c
> > > > @@ -2468,17 +2468,61 @@ static int clgi_interception(struct kvm_vcpu *vcpu)
> > > >
> > > >  static int invlpga_interception(struct kvm_vcpu *vcpu)
> > > >  {
> > > > +       struct vcpu_svm *svm = to_svm(vcpu);
> > > >         /* FIXME: Handle an address size prefix. */
> > > >         gva_t gva = kvm_rax_read(vcpu);
> > > >         u32 asid = kvm_ecx_read(vcpu);
> > > > +       int cpu;
> > > >
> > > >         if (nested_svm_check_permissions(vcpu))
> > > >                 return 1;
> > > >
> > > >         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
> > > >
> > > > -       /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
> > > > -       kvm_mmu_invlpg(vcpu, gva);
> > > > +       /*
> > > > +        * INVLPG on a non-canonical address is a NOP according to the SDM,
> > > > +        * assume the same behavior from INVLPGA since the APM doesn't specify.
> > > > +        */
> > > > +       if (is_noncanonical_invlpg_address(gva, vcpu))
> > > > +               return kvm_skip_emulated_instruction(vcpu);
> > >
> > > If L1 is in 32-bit mode with junk in RAX[63:32] (e.g. bits left over
> > > from long mode), the full 64-bit value may not be canonical. Should
> > > the kvm_rax_read(vcpu) above be kvm_register_read(vcpu,
> > > VCPU_REGS_RAX)?
> >
> > Doesn't kvm_rax_read() already use kvm_reg_mode_mask() as per
> > __BUILD_KVM_GPR_ACCESSORS()?
>
> Yes, Jim's probably thinking of older kernels before fc40b1254c32 ("KVM: x86: Add
> mode-aware versions of kvm_<reg>_{read,write}() helpers").

Doh! My bad.