Re: [PATCH 4/6] mailbox: Add AMD PL Mailbox soft IP controller

[Shah, Tanmay]

On 10/15/2026 4:48 AM, Krzysztof Kozlowski wrote:
> On Wed, Oct 14, 2026 at 02:34:24PM -0700, Ben Levinsky wrote:
>> Add a mailbox-framework controller for the AMD programmable-logic
>> Mailbox soft IP. Expose separate transmit and receive FIFO channels.
>>
>> Enable the interface clock only while a channel is started, before any
>> register access, and disable it last when the channel shuts down. Keep
>> provider probe free of register accesses and leave the IRQ disabled until
>> a client starts the receive channel. Initialize each FIFO when its channel
>> starts, use receive-threshold interrupts for incoming words, and poll the
>> send-threshold status for transmit completion. Stop that polling from
>> accessing registers once the transmit channel begins to shut down.
>>
>> Carry mailbox payloads in struct zynqmp_ipi_message, limited to the FIFO
>> depth given by the device tree. The FIFO transfers 32-bit words and the
>> hardware conveys neither a byte count nor the FIFO occupancy, so a
>> transmit length that is not a multiple of four is zero-padded to a whole
>> word.
>>
>> On a receive-threshold interrupt, read up to one FIFO depth of words and
>> deliver them as one message, then acknowledge the interrupt. The event
>> latches only when the FIFO goes from empty to nonempty, so a word that
>> arrives between the drain and the acknowledge, or words left by the
>> bounded drain, raise no new event. If the FIFO is nonempty after the
>> acknowledge, toggle the threshold to latch a new event for them.
>>
>> Assisted-by: LLM sparse
>> Signed-off-by: Ben Levinsky <ben.levinsky@xxxxxxx>
>> ---
>>  MAINTAINERS                      |   7 +
>>  drivers/mailbox/Kconfig          |  10 +
>>  drivers/mailbox/Makefile         |   1 +
>>  drivers/mailbox/amd-pl-mailbox.c | 369 +++++++++++++++++++++++++++++++
>>  4 files changed, 387 insertions(+)
>>  create mode 100644 drivers/mailbox/amd-pl-mailbox.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index f53047aa8d3c..4e28e0c311c0 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1287,6 +1287,13 @@ S:	Supported
>>  T:	git https://gitlab.freedesktop.org/agd5f/linux.git
>>  F:	drivers/gpu/drm/amd/pm/
>>  
>> +AMD PROGRAMMABLE LOGIC MAILBOX DRIVER
>> +M:	Ben Levinsky <ben.levinsky@xxxxxxx>
>> +L:	linux-kernel@xxxxxxxxxxxxxxx
>> +S:	Maintained
>> +F:	Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml
>> +F:	drivers/mailbox/amd-pl-mailbox.c
>> +
>>  AMD PSTATE DRIVER
>>  M:	Huang Rui <ray.huang@xxxxxxx>
>>  M:	Mario Limonciello <mario.limonciello@xxxxxxx>
>> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
>> index ab869769e278..3c3f262c903c 100644
>> --- a/drivers/mailbox/Kconfig
>> +++ b/drivers/mailbox/Kconfig
>> @@ -8,6 +8,16 @@ menuconfig MAILBOX
>>  
>>  if MAILBOX
>>  
>> +config AMD_PL_MAILBOX
>> +	tristate "AMD PL Mailbox soft IP controller"
> 
> Missing depends on Zynq/Xilinx.
> 
>> +	depends on HAS_IOMEM
>> +	depends on OF
>> +	help
>> +	  Mailbox controller for the AMD Programmable Logic Mailbox soft IP.
>> +	  The controller exposes transmit and receive FIFO channels to mailbox
>> +	  clients. It supports interrupt-driven receive notification and
>> +	  polling-based transmit completion through the common mailbox framework.
> 
> ...
> 
>> +	mb->controller.dev = dev;
>> +	mb->controller.ops = &amd_pl_mbox_ops;
>> +	mb->controller.chans = mb->chans;
>> +	mb->controller.num_chans = AMD_PL_MBOX_NUM_CHANS;
>> +	mb->controller.txdone_poll = true;
>> +	mb->controller.txpoll_period = 1;
>> +	mb->controller.of_xlate = amd_pl_mbox_xlate;
>> +
>> +	ret = devm_request_irq(dev, mb->irq, amd_pl_mbox_irq,
>> +			       IRQF_NO_AUTOEN,
>> +			       dev_name(dev), mb);
>> +	if (ret)
>> +		return ret;
>> +
>> +	return devm_mbox_controller_register(dev, &mb->controller);
>> +}
>> +
>> +static const struct of_device_id amd_pl_mbox_of_match[] = {
>> +	{ .compatible = "amd,zynqmp-pl-mbox-2.1" },
>> +	{ .compatible = "amd,versal-pl-mbox-2.1" },
>> +	{ .compatible = "amd,versal-net-pl-mbox-2.1" },
>> +	{ .compatible = "amd,versal2-pl-mbox-2.1" },
> 
> So all of them are compatible? Then why do you need all this?
> 

Hi Krzysztof,

This block will be used on 4 SoC - zynqmp, versal, versal-net & versal2.
IIRC we should list each SoC where the device/hw block is available.
That is why we listed all 4 of them. I am not sure if the compatible
property in the YAML is presenting this correctly, but here I think it
is good. Please suggest if there is a better way.

Thank You.

> Best regards,
> Krzysztof