Re: [PATCH v10 1/8] dt-bindings: gpio: pl061: add Ambarella CV75 variant

[Linus Walleij]

On Thu, Oct 15, 2026 at 12:54 PM Long Zhao via B4 Relay
<devnull+longzhao.ambarella.com@xxxxxxxxxx> wrote:

> From: Long Zhao <longzhao@xxxxxxxxxxxxx>
>
> The CV75 GPIO is a modified PL061. The basic registers have the same
> names and roles (DAT/DIR/IS/IBE/IEV/IE/MIS/IC). Each bank is 32-bit
> and 32 lines and adds MASK and ENABLE, so it is not
> register-compatible with the ARM PL061 and arm,pl061 must not be
> used as a fallback.
>
> The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT
> compatible string. These blocks do not implement the standard PL061 ID
> (0x00041061) in the ID registers, so arm,primecell-periphid is required
> and is fixed to 0x000e8061; the driver uses that ID to select the
> Ambarella layout. gpio-ranges is required because each bank is a slice
> of the SoC pinctrl pin space.
>
> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Signed-off-by: Long Zhao <longzhao@xxxxxxxxxxxxx>

Reviewed-by: Linus Walleij <linusw@xxxxxxxxxx>

Yours,
Linus Walleij