Re: [PATCH v3 3/3] phy: qcom-qusb2: describe autoresume bit

[Konrad Dybcio]

On 9/20/26 3:59 PM, Dmitry Baryshkov wrote:
> There is a confusion regarding the autoresume bit. Some verions of the
> QUSB2 PHY have it in the TEST1 register, while on the others it is a
> part of the TEST_CTRL register. When adding support for autoresume bit,
> the code attempted to simplify the handling of those registers, putting
> both registers to the TEST1 layout entry. In the end,
> ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
> (because platforms using that layout didn't use autoresume), while
> msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
> layout entry.
> 
> Update the platform data to specify the register to be used for
> autoresume handling, define both TEST1 and TEST_CTRL registers and merge
> ipq6018_regs_layout and msm8996_regs_layout which become identical
> afterwards.
> 
> Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> ---

GPT has a concern:

[P2] Preserve Shikra's autoresume behavior

shikra_phy_cfg uses msm8996_regs_layout but doesn't set
autoresume_disable. This adds TEST_CTRL[3] to the shared layout, so
runtime suspend will now toggle it for Shikra whenever the PHY mode
is valid. Previously, its unset autoresume_en was zero, making these
writes no-ops. Unless enabling autoresume on Shikra is intentional
and verified, preserve the old behavior by disabling it for this
configuration.

but I think that's fine since we *want* autoresume?

Konrad