Re: [PATCH 1/1] arm64: dts: qcom: glymur: Set snps,resume-hs-terminations for USB controllers

[Konrad Dybcio]

On 10/16/26 11:31 AM, Peter Chen wrote:
> On 26-10-16 11:24:05, Konrad Dybcio wrote:
>> On 10/16/26 11:13 AM, Peter Chen wrote:
>>> The DWC3 controllers on Glymur are paired with the M31 eUSB2 PHY.
>>> According to HPG, host-mode USB2 L2/L1 resume with this PHY, GUCTL1[10]
>>> (RESUME_OPMODE_HS_HOST) must be set.
>>
>> $ rg -i m31-eusb2 arch -l
>> arch/arm64/boot/dts/qcom/glymur.dtsi
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> arch/arm64/boot/dts/qcom/hawi.dtsi
>> arch/arm64/boot/dts/qcom/sm8750.dtsi
>>
>> Can you send a fixup for all of these?
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> 
> Sure, but I only have Glymur CRD, can't test this change on all hardware,
> is it okay?

The hardware programming guide says this is a necessity due to
the hw specifics. This is enough evidence - you can then ask some
of our colleagues who recently submitted support for these
SoCs to test it out.

Konrad