Re: [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU and LLCC BWMON

[Konrad Dybcio]

On 10/16/26 8:13 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@xxxxxxxxxxxxxxxxxxx>
> 
> Add the CPU-to-LLCC and LLCC-to-DDR bandwidth monitors, so that the
> interconnect votes follow the measured memory traffic.
> 
> The levels are those of the downstream llcc-bw-opp-table and
> ddr-bw-opp-table. Downstream limits two DDR levels (5161 and 8136 MB/s)
> to LPDDR4X; leave them out, as was done for SM8250.
> 
> Assisted-by: LLM
> Signed-off-by: Demeter Barna <me@xxxxxxxxxxxxxxxxxxx>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>

Konrad