Re: [PATCH] arm64: Use symbolic constants for the ccmp NZCV immediates

[Anshuman Khandual]

On Fri, Oct 09, 2026 at 08:21:47AM +0100, Fuad Tabba wrote:
> The ccmp instructions in the EL2 setup code, reset_pmuserenr_el0 and
> the hyp vectors give the flags to set when their condition fails as a
> raw NZCV immediate, #4 or #8. Which condition that leaves true for the
> branch that follows has to be worked out from the pseudocode each time.
> 
> Define CCMP_NZCV_EQ and CCMP_NZCV_LT from the PSR bits, named for the
> condition each leaves true, and pass those instead.
> 
> No functional change intended.
> 
> Suggested-by: Will Deacon <will@xxxxxxxxxx>
> Link: https://lore.kernel.org/all/asIQ1ZwUjkmNJbRP@willie-the-truck/
> Signed-off-by: Fuad Tabba <fuad.tabba@xxxxxxxxx>

Reviewed-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>

> ---
>  arch/arm64/include/asm/assembler.h | 2 +-
>  arch/arm64/include/asm/el2_setup.h | 4 ++--
>  arch/arm64/include/asm/ptrace.h    | 4 ++++
>  arch/arm64/kvm/hyp/hyp-entry.S     | 2 +-
>  4 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index 0b58b550e8dce..b4b97e03db828 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -500,7 +500,7 @@ alternative_else_nop_endif
>  	mrs	\tmpreg, id_aa64dfr0_el1
>  	ubfx	\tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
>  	cmp	\tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI
> -	ccmp	\tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
> +	ccmp	\tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #CCMP_NZCV_EQ, ne
>  	b.eq	9000f				// Skip if no PMU present or IMP_DEF
>  	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0
>  9000:
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 1da277baacf78..c0ece880e85bd 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -137,7 +137,7 @@
>  	mrs	x1, id_aa64dfr0_el1
>  	ubfx	x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
>  	cmp	x0, #ID_AA64DFR0_EL1_PMUVer_NI
> -	ccmp	x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
> +	ccmp	x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #CCMP_NZCV_EQ, ne
>  	b.eq	.Lskip_pmu_\@			// Skip if no PMU present or IMP_DEF
>  	mrs	x0, pmcr_el0			// Disable debug access traps
>  	ubfx	x0, x0, #11, #5			// to EL2 and allow access to
> @@ -422,7 +422,7 @@
>  	mrs	x1, id_aa64dfr0_el1
>  	ubfx	x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
>  	cmp	x1, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF
> -	ccmp	x1, #ID_AA64DFR0_EL1_PMUVer_V3P9, #8, ne
> +	ccmp	x1, #ID_AA64DFR0_EL1_PMUVer_V3P9, #CCMP_NZCV_LT, ne
>  	b.lt	.Lskip_pmuv3p9_\@		// Skip if < PMUv3p9 or IMP_DEF
>  
>  	orr	x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0
> diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
> index f7dc5fb9427d6..15c381ef7d2c2 100644
> --- a/arch/arm64/include/asm/ptrace.h
> +++ b/arch/arm64/include/asm/ptrace.h
> @@ -30,6 +30,10 @@
>  #define PSR_MODE_THREAD_BIT	(1 << 0)
>  #define PSR_IL_BIT		(1 << 20)
>  
> +/* CCMP NZCV immediates that make the named condition hold */
> +#define CCMP_NZCV_EQ		(PSR_Z_BIT >> 28)
> +#define CCMP_NZCV_LT		(PSR_N_BIT >> 28)
> +
>  /* AArch32-specific ptrace requests */
>  #define COMPAT_PTRACE_GETREGS		12
>  #define COMPAT_PTRACE_SETREGS		13
> diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S
> index 03f97d71984c4..8621eacd13738 100644
> --- a/arch/arm64/kvm/hyp/hyp-entry.S
> +++ b/arch/arm64/kvm/hyp/hyp-entry.S
> @@ -46,7 +46,7 @@ el1_sync:				// Guest trapped into EL2
>  	mrs	x0, esr_el2
>  	ubfx	x0, x0, #ESR_ELx_EC_SHIFT, #ESR_ELx_EC_WIDTH
>  	cmp	x0, #ESR_ELx_EC_HVC64
> -	ccmp	x0, #ESR_ELx_EC_HVC32, #4, ne
> +	ccmp	x0, #ESR_ELx_EC_HVC32, #CCMP_NZCV_EQ, ne
>  	b.ne	el1_trap
>  
>  	/*
> -- 
> 2.39.5
>