Re: [RFC PATCH 2/6] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac

From: Conor Dooley

Date: Mon Oct 05 2026 - 06:46:37 EST


On Sun, Oct 04, 2026 at 03:40:42PM +0100, Lucas Tanure wrote:
> The T7 has the same ethernet glue as the G12A, but the controller
> reaches DRAM through a pipeline stage that the hardware design inserts
> in the bus path. That stage has a gate of its own, which no other member
> of the family has. Nothing else in Linux claims the gate, so it is
> switched off as unused and the port can then no longer complete a
> transfer.
>
> Describing it means a fourth clock, and the fourth clock of the existing
> list is the one driving the timing adjustment logic. The T7 applies the
> RGMII RX delay through PRG_ETH1 and never enables that logic, so it has
> no use for that clock. Give the T7 a list of its own with the pipeline
> gate as the fourth entry, under the same name the SD/eMMC controllers of
> this SoC already use for the equivalent stage on their own bus path. All
> four entries are required, since the port cannot move data without any
> of them.
>
> The RX delay range is the one the G12A has, since it is the same
> register field.
>
> The compatible pairs the T7 name with the 5.10a Synopsys core the MAC
> reports, and with the generic fallback.
>
> Assisted-by: LLM
> Signed-off-by: Lucas Tanure <tanure@xxxxxxxxx>
> ---
> .../bindings/net/amlogic,meson-dwmac.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> index 90ef79161ab1..96118b4d1560 100644
> --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> @@ -23,6 +23,7 @@ select:
> - amlogic,meson-gxbb-dwmac
> - amlogic,meson-axg-dwmac
> - amlogic,meson-g12a-dwmac
> + - amlogic,t7-dwmac
> required:
> - compatible
>
> @@ -57,6 +58,47 @@ allOf:
> - const: clkin1
> - const: timing-adjustment
>
> + # The T7 applies the RGMII RX delay through PRG_ETH1 and never enables the
> + # timing adjustment logic, so it has no timing-adjustment clock. What it does
> + # need is the gate of the pipeline stage the controller reaches DRAM through.
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: amlogic,t7-dwmac
> + then:
> + properties:
> + clocks:
> + items:
> + - description: GMAC main clock
> + - description: First parent clock of the internal mux
> + - description: Second parent clock of the internal mux
> + - description:
> + clock of the pipeline stage inserted in the bus path between
> + the controller and the DRAM. Without it, the controller cannot
> + complete DMA transfers.

Have you checked that this actually works as a limiter to only 4 clocks?
There's an additionalItems: true in the snps,dwmac.yaml that I don't
know if will permit random additional items here.

Cheers,
Conor.

> +
> + clock-names:
> + items:
> + - const: stmmaceth
> + - const: clkin0
> + - const: clkin1
> + - const: pipeline
> +
> + # Delay definitions for Meson8b and newer (including T7)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - amlogic,meson8b-dwmac
> + - amlogic,meson8m2-dwmac
> + - amlogic,meson-gxbb-dwmac
> + - amlogic,meson-axg-dwmac
> + - amlogic,meson-g12a-dwmac
> + - amlogic,t7-dwmac
> + then:
> + properties:
> amlogic,tx-delay-ns:
> enum: [0, 2, 4, 6]
> default: 2
> @@ -106,6 +148,7 @@ allOf:
> contains:
> enum:
> - amlogic,meson-g12a-dwmac
> + - amlogic,t7-dwmac
> then:
> properties:
> rx-internal-delay-ps:
> @@ -143,6 +186,10 @@ properties:
> - amlogic,meson6-dwmac
> - amlogic,meson8m2-dwmac
> - const: snps,dwmac
> + - items:
> + - const: amlogic,t7-dwmac
> + - const: snps,dwmac-5.10a
> + - const: snps,dwmac
>
> reg:
> items:
> --
> 2.56.0
>

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