[PATCH v4 04/15] iio: adc: xilinx-xadc: Drop unnecessary masking and dead code
From: Dileep Kumar Nagavarapu
Date: Mon Oct 05 2026 - 05:44:28 EST
Remove a no-operation bitwise-OR with zero (dead code) and the redundant
16-bit masking when storing values into u16 destinations, where the
mask has no effect. Also remove the unused macros.
No functional change intended.
Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@xxxxxxx>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@xxxxxxx>
Signed-off-by: Dileep Kumar Nagavarapu <dileepkumar.nagavarapu@xxxxxxx>
---
drivers/iio/adc/xilinx-xadc-core.c | 24 ++--------------------
drivers/iio/adc/xilinx-xadc.h | 33 ------------------------------
2 files changed, 2 insertions(+), 55 deletions(-)
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index 1c60d4f38ffe..b4a3e6f967c4 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -47,35 +47,20 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
#define XADC_ZYNQ_REG_CTL 0x18
#define XADC_ZYNQ_CFG_ENABLE BIT(31)
-#define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
-#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
-#define XADC_ZYNQ_CFG_WEDGE BIT(13)
#define XADC_ZYNQ_CFG_REDGE BIT(12)
#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
-#define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
#define XADC_ZYNQ_CFG_IGAP(x) (x)
-#define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
#define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
#define XADC_ZYNQ_INT_ALARM_MASK 0xff
-#define XADC_ZYNQ_INT_ALARM_OFFSET 0
-#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
-#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
-#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
-#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
-#define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
-#define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
-#define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
#define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
-#define XADC_ZYNQ_STATUS_OT BIT(7)
-#define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
#define XADC_ZYNQ_CTL_RESET BIT(4)
@@ -87,10 +72,6 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
/* AXI register definitions */
#define XADC_AXI_REG_RESET 0x00
-#define XADC_AXI_REG_STATUS 0x04
-#define XADC_AXI_REG_ALARM_STATUS 0x08
-#define XADC_AXI_REG_CONVST 0x0c
-#define XADC_AXI_REG_XADC_RESET 0x10
#define XADC_AXI_REG_GIER 0x5c
#define XADC_AXI_REG_IPISR 0x60
#define XADC_AXI_REG_IPIER 0x68
@@ -182,7 +163,6 @@ static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
- tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
@@ -230,7 +210,7 @@ static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
- *val = resp & 0xffff;
+ *val = resp;
return 0;
}
@@ -452,7 +432,7 @@ static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
u32 val32;
xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, &val32);
- *val = val32 & 0xffff;
+ *val = val32;
return 0;
}
diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
index fb911ed87600..8449fb741370 100644
--- a/drivers/iio/adc/xilinx-xadc.h
+++ b/drivers/iio/adc/xilinx-xadc.h
@@ -130,21 +130,6 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
#define XADC_REG_VCCO_DDR 0x0f
#define XADC_REG_VAUX(x) (0x10 + (x))
-#define XADC_REG_MAX_TEMP 0x20
-#define XADC_REG_MAX_VCCINT 0x21
-#define XADC_REG_MAX_VCCAUX 0x22
-#define XADC_REG_MAX_VCCBRAM 0x23
-#define XADC_REG_MIN_TEMP 0x24
-#define XADC_REG_MIN_VCCINT 0x25
-#define XADC_REG_MIN_VCCAUX 0x26
-#define XADC_REG_MIN_VCCBRAM 0x27
-#define XADC_REG_MAX_VCCPINT 0x28
-#define XADC_REG_MAX_VCCPAUX 0x29
-#define XADC_REG_MAX_VCCO_DDR 0x2a
-#define XADC_REG_MIN_VCCPINT 0x2c
-#define XADC_REG_MIN_VCCPAUX 0x2d
-#define XADC_REG_MIN_VCCO_DDR 0x2e
-
#define XADC_REG_CONF0 0x40
#define XADC_REG_CONF1 0x41
#define XADC_REG_CONF2 0x42
@@ -152,18 +137,13 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
#define XADC_REG_INPUT_MODE(x) (0x4c + (x))
#define XADC_REG_THRESHOLD(x) (0x50 + (x))
-#define XADC_REG_FLAG 0x3f
-
#define XADC_CONF0_EC BIT(9)
-#define XADC_CONF0_ACQ BIT(8)
#define XADC_CONF0_MUX BIT(11)
#define XADC_CONF0_CHAN(x) (x)
#define XADC_CONF1_SEQ_MASK (0xf << 12)
#define XADC_CONF1_SEQ_DEFAULT (0 << 12)
-#define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12)
#define XADC_CONF1_SEQ_CONTINUOUS (2 << 12)
-#define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12)
#define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12)
#define XADC_CONF1_SEQ_INDEPENDENT (8 << 12)
#define XADC_CONF1_ALARM_MASK 0x0f0f
@@ -176,7 +156,6 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
#define XADC_CONF2_PD_ADC_B (0x2 << 4)
#define XADC_CONF2_PD_BOTH (0x3 << 4)
-#define XADC_ALARM_TEMP_MASK BIT(0)
#define XADC_ALARM_VCCINT_MASK BIT(1)
#define XADC_ALARM_VCCAUX_MASK BIT(2)
#define XADC_ALARM_OT_MASK BIT(3)
@@ -189,17 +168,5 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
#define XADC_THRESHOLD_VCCINT_MAX 0x1
#define XADC_THRESHOLD_VCCAUX_MAX 0x2
#define XADC_THRESHOLD_OT_MAX 0x3
-#define XADC_THRESHOLD_TEMP_MIN 0x4
-#define XADC_THRESHOLD_VCCINT_MIN 0x5
-#define XADC_THRESHOLD_VCCAUX_MIN 0x6
-#define XADC_THRESHOLD_OT_MIN 0x7
-#define XADC_THRESHOLD_VCCBRAM_MAX 0x8
-#define XADC_THRESHOLD_VCCPINT_MAX 0x9
-#define XADC_THRESHOLD_VCCPAUX_MAX 0xa
-#define XADC_THRESHOLD_VCCODDR_MAX 0xb
-#define XADC_THRESHOLD_VCCBRAM_MIN 0xc
-#define XADC_THRESHOLD_VCCPINT_MIN 0xd
-#define XADC_THRESHOLD_VCCPAUX_MIN 0xe
-#define XADC_THRESHOLD_VCCODDR_MIN 0xf
#endif
--
2.34.1