Re: [PATCH net-next] net: stmmac: mask the MAC interrupt while resume resets the MAC

[Igor Velkov]

On Thu, Oct 01, 2026 at 02:40:46PM +0200, Andrew Lunn wrote:
> For my understanding, it is the hardware reset which clears the mask,
> not software?
>
> If it is hardware, that is an odd hardware design.

Yes, the hardware: dwmac_dma_reset() sets SWR in DMA_BUS_MODE and the
MAC returns its registers to their reset values. On dwmac1000
GMAC_INT_MASK is a mask register, so its reset value 0 unmasks
everything; dwmac4 has an enable register (GMAC_INT_EN) instead.

A correction to the v1 text: no link change is needed. RGSMIIIS was
already pending before the reset (Helios64, SWR written from a test
script on the running board: int_status 0x1 under int_mask 0x1; after
it int_mask 0, DMA status 0x04000000). Nothing on the RGMII path reads
0xd8, which would clear it, so it stays pending from the first link
change on.

dwmac1000_core_init() rewrites the mask shortly after, from the same
resume thread. When that thread runs on the CPU that takes the MAC
interrupt, the storm starves it: with both on one CPU the storm hit
the first resume on Helios64, ROCK Pi 4A and ODROID-HC4; on different
CPUs it printed at most 3 messages per resume in 30 resumes.

v2 for net, with the description fixed and a Fixes tag:
https://lore.kernel.org/r/20261002043558.1302590-1-iav@xxxxxx

--
Igor Velkov