Re: [PATCH v2] Revert "PCI: layerscape: Change default error response behavior"

[Frank Li]

On Thu, Oct 01, 2026 at 11:33:23AM -0400, Jeff Barnes wrote:
> [You don't often get email from jeffbarnes@xxxxxxxxxxxxxxxxxxx. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> This reverts commit 84d897d69938
> ("PCI: layerscape: Change default error response behavior").
>
> The Layerscape PCIe driver programs the DesignWare
> AMBA_ERROR_RESPONSE_DEFAULT register at offset 0x8d0 with 0x9401.
>
> For AXI, the documented default with AMBA_ERROR_RESPONSE_GLOBAL cleared
> returns OKAY with all-ones data for errors on non-posted requests.
> Setting AMBA_ERROR_RESPONSE_GLOBAL causes an AXI error response instead,
> with AMBA_ERROR_RESPONSE_MAP selecting SLVERR or DECERR for individual
> PCIe completion errors.
>
> The value 0x9401 sets AMBA_ERROR_RESPONSE_GLOBAL and maps Unsupported
> Request, Completer Abort, and Completion Timeout to SLVERR.
>
> A PCI configuration access can race with the link going down after
> dw_pcie_other_conf_map_bus() checks the link but before
> pci_generic_config_read() performs the MMIO access. If the transaction
> results in a Completion Timeout, the Layerscape error response setting
> propagates it to AXI as SLVERR, resulting in an asynchronous SError and
> kernel panic.
>
> Reproduce the race by obtaining the configuration-space mapping while
> the link is up, then disabling the link from another CPU immediately
> before performing the MMIO configuration read.
>
> With the error response override enabled, the overlapping configuration
> read results in an asynchronous SError and kernel panic. With the
> DesignWare default behavior restored, the same test returns 0xffffffff.
> AER reports a non-fatal Completion Timeout, and no SError or kernel
> panic occurs.
>
> Restore the documented DesignWare default error response behavior so a
> failed non-posted PCIe transaction does not become a fatal AXI error.
>
> Fixes: 84d897d69938 ("PCI: layerscape: Change default error response behavior")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Jeff Barnes <jeffbarnes@xxxxxxxxxxxxxxxxxxx>
>

---

should be here, maintainer should can handle this for you.

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>.

> Changes in v2:
> - Change the subject to identify this as a revert, as requested by
>   Frank Li.
> - Document the DesignWare AMBA_ERROR_RESPONSE_DEFAULT behavior and
>   decode the 0x9401 setting used by Layerscape.
> - Clarify that the setting propagates Completion Timeout as AXI SLVERR
>   rather than causing the underlying PCIe transaction failure.
>
> ---
>  drivers/pci/controller/dwc/pci-layerscape.c | 12 ------------
>  1 file changed, 12 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
> index 14d6ac4fc53f..d333f1ae8a41 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape.c
> @@ -28,8 +28,6 @@
>
>  /* PEX Internal Configuration Registers */
>  #define PCIE_STRFMR1           0x71c /* Symbol Timer & Filter Mask Register1 */
> -#define PCIE_ABSERR            0x8d0 /* Bridge Slave Error Response Register */
> -#define PCIE_ABSERR_SETTING    0x9401 /* Forward error of non-posted request */
>
>  /* PF Message Command Register */
>  #define LS_PCIE_PF_MCR         0x2c
> @@ -103,14 +101,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
>         iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
>  }
>
> -/* Forward error response of outbound non-posted requests */
> -static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
> -{
> -       struct dw_pcie *pci = pcie->pci;
> -
> -       iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
> -}
> -
>  static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)
>  {
>         if (pcie->big_endian)
> @@ -180,8 +170,6 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp)
>         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>         struct ls_pcie *pcie = to_ls_pcie(pci);
>
> -       ls_pcie_fix_error_response(pcie);
> -
>         dw_pcie_dbi_ro_wr_en(pci);
>         ls_pcie_clear_multifunction(pcie);
>         dw_pcie_dbi_ro_wr_dis(pci);
> --
> 2.43.0
>