[PATCH net 0/2] dpll: zl3073x: fix output pin esync and sibling notifications

[Ivan Vecera]

This series fixes two issues in the zl3073x output pin handling.

Patch 1 makes the embedded sync (eSync) configuration follow the output
carrier frequency. Changing an output pin's frequency did not update its
eSync period/width, so eSync ran at the wrong rate and, for a 1 Hz
carrier, could get stuck on because esync_get() hides it.

Patch 2 notifies the sibling pin of an output pair when a shared HW
setting (divisor, clock type, eSync period/width, phase compensation) is
changed through one pin, so userspace listening on the sibling pin sees
the change. It also serializes access to the per-DPLL pin list, which the
new sibling lookup walks, against pin registration and teardown.

Ivan Vecera (2):
  dpll: zl3073x: make embedded sync follow the output carrier frequency
  dpll: zl3073x: notify sibling pin when shared output config changes

 drivers/dpll/zl3073x/dpll.c | 192 +++++++++++++++++++++++++-----------
 drivers/dpll/zl3073x/out.h  |  36 +++++++
 2 files changed, 173 insertions(+), 55 deletions(-)

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2.55.0