[PATCH 16/16] ARM: dts: renesas: r9a06g032: Describe the EIP-150 block

[Miquel Raynal (Schneider Electric)]

The EIP-150 is composed of 3 blocks:
* An interrupt controller named EIP-201 AIC
    - fed by a clock coming from the EIP-150
    - connected to the main GIC
* A random number generator named EIP-76
    - fed by a clock coming from the EIP-150
    - signalling interrupts through the AIC
* A public key accelerator engine named EIP-28
    - Fed by a clock coming from the EIP-150
    - Signalling interrupts through the AIC

Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@xxxxxxxxxxx>
---
 arch/arm/boot/dts/renesas/r9a06g032.dtsi | 42 ++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index f4f760aff28b..6aaa93ed03d6 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+#include <dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h>
 
 / {
 	compatible = "renesas,r9a06g032";
@@ -170,6 +171,47 @@ usb@2,0 {
 			};
 		};
 
+		eip150: bus@40040000 {
+			compatible = "inside-secure,safexcel-eip150", "simple-pm-bus";
+			clocks = <&sysctrl R9A06G032_HCLK_CRYPTO_EIP150>;
+			#clock-cells = <0>;
+			clock-map = <&sysctrl R9A06G032_HCLK_CRYPTO_EIP150>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x40040000 0x40040000 0x10000>;
+			status = "disabled";
+
+			eip76_rng: rng@40040000 {
+				compatible = "inside-secure,safexcel-eip76";
+				reg = <0x40040000 0x80>;
+				interrupt-parent = <&eip201_aic>;
+				interrupts = <AIC_TRNG_INT IRQ_TYPE_EDGE_RISING>;
+				clocks = <&eip150>;
+				status = "disabled";
+			};
+
+			eip28_pka: crypto@40044000 {
+				compatible = "inside-secure,safexcel-eip28";
+				reg = <0x40044000 0x4000>;
+				interrupt-parent = <&eip201_aic>;
+				interrupts = <AIC_PKA_INT0 IRQ_TYPE_EDGE_RISING>,
+					     <AIC_PKA_INT1 IRQ_TYPE_EDGE_RISING>,
+					     <AIC_PKA_INT2 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&eip150>;
+				status = "disabled";
+			};
+
+			eip201_aic: interrupt-controller@40048000 {
+				compatible = "inside-secure,safexcel-eip201";
+				reg = <0x40048000 0x4000>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&eip150>;
+				status = "disabled";
+			};
+		};
+
 		uart0: serial@40060000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 			reg = <0x40060000 0x400>;

-- 
2.51.1