Re: [PATCH] mm/slab: align kmalloc to cacheline when DMA API debugging is active

[Mikhail Gavrilov]

On Fri, Mar 27, 2026 at 1:00 PM Harry Yoo (Oracle) <harry@xxxxxxxxxx> wrote:
>
> But dma_get_cache_alignment() < L1_CACHE_BYTES means the architecture
> actually allows overlapping cachelines, no?

Hi Harry,

On x86_64, dma_get_cache_alignment() returns L1_CACHE_BYTES (both
are 64).  The condition (dma_get_cache_alignment() < L1_CACHE_BYTES)
would be false, so the check wouldn't suppress the warning.

The problem isn't that the architecture allows overlapping -- it's
that kmalloc returns 8-byte aligned buffers that happen to land in
the same 64-byte cacheline.  The DMA debug code correctly identifies
that two DMA mappings share a cacheline, but on coherent platforms
this is harmless.

Adding a dev_is_dma_coherent() check in dma-debug would fix x86 but
would also silence the warning for any coherent device, including
ones behind IOMMUs that might have non-coherent paths.  That's why
Alan's conclusion was that fixing the allocator side is safer --
it doesn't weaken any debug checks, it just ensures the situation
never arises.

-- 
Best Regards,
Mike Gavrilov.