RE: [PATCH v8 01/11] dt-bindings: clock: Document RZ/G3L SoC

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 26 March 2026 18:24
> Subject: Re: [PATCH v8 01/11] dt-bindings: clock: Document RZ/G3L SoC
> 
> Hi Biju,
> 
> On Tue, 24 Mar 2026 at 12:43, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5
> > clocks compared to 1 clock on other SoCs.
> >
> > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clocks, as
> > listed in section 4.4.4.1 ("Block Diagram of the Clock System"),
> > module clock outputs, as listed in section 4.4.2 ("Clock List r1.00")
> > and add Reset definitions referring to registers CPG_RST_* in Section
> > 4.4.3
> > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> >
> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> 
> Missing "renesas," prefix.

Oops, missed it.

> 
> > @@ -0,0 +1,342 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> 
> Missing RENESAS_ infix.
> 
> Will fix accordingly while applying.

Thank you for taking care.

Cheers,
Biju