[PATCH v2] pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers

From: Biju

Date: Wed Mar 25 2026 - 14:29:59 EST


From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

The rzg2l_pinctrl_pm_setup_regs() handles save/restore of
{IOLH,IEN,PUPD,SMT} registers during s2ram, but only for ports where all
pins share the same pincfg. Extend the code to also support ports with
variable pincfg per pin, so that {IOLH,IEN,PUPD,SMT} registers are
correctly saved and restored for all pins.

Fixes: 254203f9a94c ("pinctrl: renesas: rzg2l: Add suspend/resume support")
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v1->v2:
* Updated commit description
* Improved the logic.
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 863e779dda02..e20d199833ee 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3001,9 +3001,12 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
{
u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
+ u32 pin_off = 0;

- for (u32 port = 0; port < nports; port++) {
+ for (u32 port = 0; port < nports; port++, pin_off += RZG2L_PINS_PER_PORT) {
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[pin_off];
bool has_iolh, has_ien, has_pupd, has_smt;
+ u64 *pin_data = pin_desc->drv_data;
u32 off, caps;
u8 pincnt;
u64 cfg;
@@ -3012,6 +3015,11 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));

+ if (cfg & RZG2L_VARIABLE_CFG) {
+ for (unsigned int i = 1; i < RZG2L_PINS_PER_PORT; i++)
+ cfg |= *pin_data++;
+ }
+
caps = FIELD_GET(PIN_CFG_MASK, cfg);
has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
has_ien = !!(caps & PIN_CFG_IEN);
--
2.43.0