Re: [PATCH 11/22] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support

[Kuninori Morimoto]

Hi John

> > I don't think we need RSND_SSI_ALWAYS_BUSIF, because PIO is used for debug
> > purpose when new SoC has comming.
> > 
> 
> I understand that PIO is useful as a debug fallback when bringing up new SoCs.
> Looking at the RZ/G3E datasheet (section 8.5), SSITDR/SSIRDR exist as data
> buffers in the SSI block, but they are accessible only through the DMA access
> port - not through the register access port (CPU access).
> 
> The datasheet explicitly states "PIO access (setting prohibited)" for the
> BUSIF data path. This is also why the register descriptions (8.5.2.3.29–33)
> list SSICR, SSISR, SSIWSR, SSIFMR, SSIFSR but no SSITDR/SSIRDR at register
> access port offsets. So PIO mode (CPU reading/writing SSITDR/SSIRDR directly)
> is not supported by the hardware.
> 
> If we attempt PIO fallback on RZ/G3E, rsnd_ssi_pio_interrupt() would try to
> access SSITDR/SSIRDR which are not mapped in the regmap, causing a failure.
> 
> So, should I keep RSND_SSI_ALWAYS_BUSIF to express this, or would you prefer
> a direct rsnd_is_rzg3e() check in rsnd_ssi_use_busif()? I would go for the
> first option as this could be reusable on other SoCs and avoid SoC-specific
> checks across functional code.

PIO is a feature which can be enabled in very specific circumstances.
It is enabled if you required, and will not be enabled unintentionally.
If it happens, it is just bug.

Thank you for your help !!

Best regards
---
Kuninori Morimoto