Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Konrad Dybcio]

On 3/23/26 8:25 PM, Dmitry Baryshkov wrote:
> On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
>> According to internal documentation, the UFS AXI PHY clock requires
>> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
>> the UFS controller fails when operating in MCQ mode, which is already
>> enabled in the device tree.
>>
>> The UFS PHY ICE core clock already has this bit set, so apply the same
>> configuration to the UFS PHY AXI clock.
>>
>> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
>> Reported-by: Nitin Rawat <nitin.rawat@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
>> ---
>>  drivers/clk/qcom/gcc-eliza.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> 
> Do we need to apply the same fix to any other platform?

FWIW on msm-5.10 (8450 kernel, from before-MCQ times) there's this
excerpt in ufs-qcom.c:


static void ufs_qcom_force_mem_config(struct ufs_hba *hba)
{
        struct ufs_clk_info *clki;

        /*
         * Configure the behavior of ufs clocks core and peripheral
         * memory state when they are turned off.
         * This configuration is required to allow retaining
         * ICE crypto configuration (including keys) when
         * core_clk_ice is turned off, and powering down
         * non-ICE RAMs of host controller.
         *
         * This is applicable only to gcc clocks.
         */
        list_for_each_entry(clki, &hba->clk_list_head, list) {

                /* skip it for non-gcc (rpmh) clocks */
                if (!strcmp(clki->name, "ref_clk"))
                        continue;

                if (!strcmp(clki->name, "core_clk_ice") ||
                        !strcmp(clki->name, "core_clk_ice_hw_ctl"))
                        qcom_clk_set_flags(clki->clk, CLKFLAG_RETAIN_MEM);
                else
                        qcom_clk_set_flags(clki->clk, CLKFLAG_NORETAIN_MEM);
                qcom_clk_set_flags(clki->clk, CLKFLAG_NORETAIN_PERIPH);
                qcom_clk_set_flags(clki->clk, CLKFLAG_PERIPH_OFF_CLEAR);
        }
}


i.e.:

* force_mem_core(true) for ICE, force_mem_core(false) otherwise
* set_force_periph_on(false) for all
* set_force_periph_off(false) for all


Notably, the Adreno driver messes with some of these settings too, as does
the DWC3 one. Older kernels (msm-4.19) also do so in MDSS, GDSC, CVP, 
camera MMC, PCIe drivers

Konrad